Intel SL8K2 Specification Update - Page 69

L2 Cache ECC Machine Check Errors May be erroneously Reported after an

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Errata R R114. Upper 32 bits of 'From' Address Reported through LBR or LER MSRs, BTMs or BTSs May be Incorrect Problem: When a far transfer switches the processor from IA-32e mode to 32-bit mode, the upper 32 bits of the 'From' (source) addresses reported through the LBR (Last Branch) or LER (Last Exception Record) MSRs (Model-Specific Registers), BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect. Implication: The upper 32 bits of the 'From' address debug information reported through LBR or LER MSRs, BTMs or BTSs may be incorrect. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R115. VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with HyperThreading Enabled Problem: When transitioning from a 64-bit host environment to a 32-bit guest environment via a VMEntry, internal conditions in a processor with Hyper-Threading enabled may cause a speculative pagetable walk to be prematurely terminated, resulting in a processor hang and the assertion of IERR#. Implication: An IERR# may occur on VMEntry from a 64-bit to a 32-bit environment with Hyper-Threading enabled. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R116. L2 Cache ECC Machine Check Errors May be erroneously Reported after an Asynchronous RESET# Assertion Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC machine-check errors when cache transactions are in-flight and RESET# is asserted: •Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153) •L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145) Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has not observed this erratum on any commercially available system. Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid error will normally be logged in the IA32_MC0_STATUS register. BIOS may clear IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific errors when IA32_MC0_STATUS does not have its VAL flag set. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 69

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
69
R114.
Upper 32 bits of ‘From’ Address Reported through LBR or LER MSRs,
BTMs or BTSs May be Incorrect
Problem:
When a far transfer switches the processor from IA-32e mode to 32-bit mode, the upper 32 bits of
the ‘From’ (source) addresses reported through the LBR (Last Branch) or LER (Last Exception
Record) MSRs (Model-Specific Registers), BTMs (Branch Trace Messages) or BTSs (Branch
Trace Stores) may be incorrect.
Implication:
The upper 32 bits of the ‘From’ address debug information reported through LBR or LER MSRs,
BTMs or BTSs may be incorrect.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R115.
VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with Hyper-
Threading Enabled
Problem:
When transitioning from a 64-bit host environment to a 32-bit guest environment via a VMEntry,
internal conditions in a processor with Hyper-Threading enabled may cause a speculative page-
table walk to be prematurely terminated, resulting in a processor hang and the assertion of IERR#.
Implication:
An IERR# may occur on VMEntry from a 64-bit to a 32-bit environment with Hyper-Threading
enabled.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R116.
L2 Cache ECC Machine Check Errors May be erroneously Reported after an
Asynchronous RESET# Assertion
Problem:
Machine check status MSRs may incorrectly report the following L2 Cache ECC machine-check
errors when cache transactions are in-flight and RESET# is asserted:
•Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
•L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Implication:
Uncorrected or corrected L2 ECC machine check errors may be erroneously reported.
Intel has
not observed this erratum on any commercially available system.
Workaround:
When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid error will
normally be logged in the IA32_MC0_STATUS register.
BIOS may clear IA32_MC2_STATUS
and/or IA32_MC1_STATUS for these specific errors when IA32_MC0_STATUS does not have
its VAL flag set.
Status:
For the steppings affected, see the
Summary Tables of Changes
.