Dell PowerEdge R7525 EMC Installation and Service Manual - Page 84

Table 36. Memory population rules, A{1}

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configuration, or operate with reduced memory. This section provides information on the memory population rules and about the nonuniform memory access (NUMA) for single or dual processor system. The memory bus may operate at speeds of 3200 MT/s, 2933 MT/s, or 2666 MT/s depending on the following factors: • System profile selected (for example, Performance Optimized, or Custom [can be run at high speed or lower]) • Maximum supported DIMM speed of the processors • Maximum supported speed of the DIMMs NOTE: MT/s indicates DIMM speed in MegaTransfers per second. The system supports Flexible Memory Configuration, enabling the system to be configured and run in any valid chipset architectural configuration. The following are the recommended guidelines for installing memory modules: • All DIMMs must be DDR4. • Mixing of memory module capacities in a system is not supported. • If memory modules with different speeds are installed, they operate at the speed of the slowest installed memory module(s). • Populate memory module sockets only if a processor is installed. ○ For single-processor systems, sockets A1 to A16 are available. ○ For dual-processor systems, sockets A1 to A16 and sockets B1 to B16 are available. ○ In Optimizer Mode, the DRAM controllers operate independently in the 64-bit mode and provide optimized memory performance. Table 36. Memory population rules Processor Configuration Memory population Memory population information Single processor Optimizer (Independent channel) population order A{1}, A{2}, A{3}, A{4}, A{5}, A{6}, A{7}, A{8}, A{9}, A{10}, A{11}, A{12}, A{13}, A{14}, A{15}, A{16} Odd amount of DIMMs per processor allowed. Dual processor (Start with processor1. Processor 1 and processor 2 population should match) Optimizer (Independent channel) population order A{1}, B{1}, A{2}, B{2}, A{3}, B{3}, A{4}, B{4}, A{5}, B{5}, A{6}, B{6}, A{7}, B{7} A{8}, B{8} Odd amount of DIMMs per processor is allowed. DIMMs must be populated identically per processor. • Populate all the sockets with white release tabs first, followed by the black release tabs. • In a dual-processor configuration, the memory configuration for each processor must be identical. For example, if you populate socket A1 for processor 1, then populate socket B1 for processor 2, and so on. • Unbalanced or odd memory configuration results in a performance loss and system may not identify the memory modules being installed, so always populate memory channels identically with equal DIMMs for best performance. • Minimum recommended configuration is to populate four equal memory modules per processor. AMD recommends limiting processors in that system to 32 cores or less. • Populate eight equal memory modules per processor (one DIMM per channel) at a time to maximize performance. NOTE: Equal memory modules refer to DIMMs with identical electrical specification and capacity that may be from different vendors. Memory interleaving with Non-uniform memory access (NUMA) Non-uniform memory access (NUMA) is a memory design used in multi-processing, where the memory access time depends on the memory location relative to the processor. In NUMA, a processor can access its own local memory faster than the non-local memory. NUMA nodes per socket (NPS) is a new feature added that allows you to configure the memory NUMA domains per socket. The configuration can consist of one whole domain (NPS1), two domains (NPS2), or four domains (NPS4). In the case of a two-socket platform, an additional NPS profile is available to have whole system memory to be mapped as single NUMA domain (NPS0). For more information on the memory interleaving for NPSx, see the Memory interleaving population rules section in this topic. BIOS implementation for NPSx • The BIOS Setup menu presents the applicable NPSx options based on the underlying model number. A change to the current NPSx is communicated to pre-BIOS firmware to take effect on the next boot. The default NPS setting is 1. • During boot, if the selected NPSx option is not allowed for the model number (for example, if the processor model number changes between reboot), system will halt at the end of POST with UEFI0388 message displayed. On the next reboot, the system will fall back to NPS1 default setting. • During boot, if the preferred interleaving for the current NPSx is not possible due to memory configuration (for example, the memory population is inconsistent with the preferred interleaving), BIOS shows a warning message UEFI0391. 84 Installing and removing system components

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configuration, or operate with reduced memory. This section provides information on the memory population rules and about the non-
uniform memory access (NUMA) for single or dual processor system.
The memory bus may operate at speeds of 3200 MT/s, 2933 MT/s, or 2666 MT/s depending on the following factors:
System profile selected (for example, Performance Optimized, or Custom [can be run at high speed or lower])
Maximum supported DIMM speed of the processors
Maximum supported speed of the DIMMs
NOTE:
MT/s indicates DIMM speed in MegaTransfers per second.
The system supports Flexible Memory Configuration, enabling the system to be configured and run in any valid chipset architectural
configuration. The following are the recommended guidelines for installing memory modules:
All DIMMs must be DDR4.
Mixing of memory module capacities in a system is not supported.
If memory modules with different speeds are installed, they operate at the speed of the slowest installed memory module(s).
Populate memory module sockets only if a processor is installed.
For single-processor systems, sockets A1 to A16 are available.
For dual-processor systems, sockets A1 to A16 and sockets B1 to B16 are available.
In Optimizer Mode, the DRAM controllers operate independently in the 64-bit mode and provide optimized memory performance.
Table 36. Memory population rules
Processor
Configuration
Memory population
Memory population
information
Single processor
Optimizer (Independent
channel) population order
A{1}, A{2}, A{3}, A{4}, A{5}, A{6},
A{7}, A{8}, A{9}, A{10}, A{11},
A{12}, A{13}, A{14}, A{15}, A{16}
Odd amount of DIMMs per
processor allowed.
Dual processor (Start with
processor1. Processor 1 and
processor 2 population
should match)
Optimizer (Independent
channel) population order
A{1}, B{1}, A{2}, B{2}, A{3}, B{3},
A{4}, B{4}, A{5}, B{5}, A{6}, B{6},
A{7}, B{7} A{8}, B{8}
Odd amount of DIMMs per
processor is allowed. DIMMs
must be populated
identically per processor.
Populate all the sockets with white release tabs first, followed by the black release tabs.
In a dual-processor configuration, the memory configuration for each processor must be identical.
For example, if you populate socket A1 for processor 1, then populate socket B1 for processor 2, and so on.
Unbalanced or odd memory configuration results in a performance loss and system may not identify the memory modules being
installed, so always populate memory channels identically with equal DIMMs for best performance.
Minimum recommended configuration is to populate four equal memory modules per processor. AMD recommends limiting processors
in that system to 32 cores or less.
Populate eight equal memory modules per processor (one DIMM per channel) at a time to maximize performance.
NOTE:
Equal memory modules refer to DIMMs with identical electrical specification and capacity that may be from
different vendors.
Memory interleaving with Non-uniform memory access (NUMA)
Non-uniform memory access (NUMA) is a memory design used in multi-processing, where the memory access time depends on the
memory location relative to the processor. In NUMA, a processor can access its own local memory faster than the non-local memory.
NUMA nodes per socket (NPS) is a new feature added that allows you to configure the memory NUMA domains per socket. The
configuration can consist of one whole domain (NPS1), two domains (NPS2), or four domains (NPS4). In the case of a two-socket
platform, an additional NPS profile is available to have whole system memory to be mapped as single NUMA domain (NPS0). For more
information on the memory interleaving for NPSx, see the Memory interleaving population rules section in this topic.
BIOS implementation for NPSx
The BIOS Setup menu presents the applicable NPSx options based on the underlying model number. A change to the current NPSx is
communicated to pre-BIOS firmware to take effect on the next boot. The default NPS setting is 1.
During boot, if the selected NPSx option is not allowed for the model number (for example, if the processor model number changes
between reboot), system will halt at the end of POST with UEFI0388 message displayed. On the next reboot, the system will fall back
to NPS1 default setting.
During boot, if the preferred interleaving for the current NPSx is not possible due to memory configuration (for example, the memory
population is inconsistent with the preferred interleaving), BIOS shows a warning message UEFI0391.
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Installing and removing system components