Brother International HL-720 Service Manual - Page 106

A 10Kbit FIFO is includedrporated., TIMER 3 Watch Dog

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1.3.2 ASIC The ASIC is composed of a Cell Based IC and has the following function blocks. (1) Oscillator circuit Generates the main clock for the CPU by dividing the source clock frequency by two. (2) Address Generator This controls the address buss by latching the AD buss signals with the ALE signal. (3) Address decoder Generates the CS for each device. (4) DRAM control Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the memory refresh processing (CAS before RAS self-refreshing method). (5) Interrupt control Interrupt levels: Priority High 9 8 7 6 5 4 3 2 Low 1 TIMER 3 (Watch Dog) MONITOR FIFO EXINT TIMER1 BD Spare CDCC / BOISE / DATA EXTENTION TIMER 2 All the interrupts can be masked. (6) Timers The following timers are included: Timer 1 16-bit timer Timer 2 10-bit timer Timer 3 Watch-dog timer (7) FIFO A 10Kbit FIFO is includedrporated. Data for one raster is transferred from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle is 6.13 Mhz. II-4

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II-4
1.3.2
ASIC
The ASIC is composed of a Cell Based IC and has the following function blocks.
(1)
Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency by
two.
(2)
Address Generator
This controls the address buss by latching the AD buss signals with the ALE
signal.
(3)
Address decoder
Generates the CS for each device.
(4)
DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the
memory refresh processing (CAS before RAS self-refreshing method).
(5) Interrupt control
Interrupt levels:
Priority
High
9
TIMER 3 (Watch Dog)
8
MONITOR
7
FIFO
6
EXINT
5
TIMER1
4
BD
3
Spare
2
CDCC / BOISE / DATA EXTENTION
Low
1
TIMER 2
All the interrupts can be masked.
(6)
Timers
The following timers are included:
Timer 1
16-bit timer
Timer 2
10-bit timer
Timer 3
Watch-dog timer
(7)
FIFO
A 10Kbit FIFO is includedrporated.
Data for one raster is transferred from the
RAM to the FIFO by DMA transmission and is output as serial video data. The
data cycle is 6.13 Mhz.