Brother International HL-720 Service Manual - Page 27

Cdcc / Boise / Data Extention, Exintoption Serial I/o

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The ASIC is composed of Cell Based IC and has the following function blocks. (1) Oscillator circuit Generates the main clock for the CPU by dividing the source clock frequency into two. (2) Address decoder Generates the CS for each device. (3) DRAM control Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls refresh recessing (CAS before RAS self-refreshing method). (4) Interrupt control Interrupt levels: Priority High 7 6 5 4 3 2 Low 1 NMI FIFO EXINT(Option Serial I/O) BD / Timer 1 SCANINT CDCC / BOISE / DATA EXTENTION Timer 2 (5) Timers The following timers are incorporated: Timer 1 Timer 2 Timer 3 16-bit timer 10-bit timer Watch-dog timer (6) FIFO A 5,120-bit FIFO is incorporated. Data for one raster is transferred from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle is 6.13 MHz. II-10

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II-10
<HL-730/730Plus>
The ASIC is composed of Cell Based IC and has the following function blocks.
(1)
Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency into
two.
(2)
Address decoder
Generates the CS for each device.
(3)
DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls
refresh recessing (CAS before RAS self-refreshing method).
(4)
Interrupt control
Interrupt levels:
Priority High
7
NMI
6
FIFO
5
EXINT(Option Serial I/O)
4
BD / Timer 1
3
SCANINT
2
CDCC / BOISE / DATA EXTENTION
Low
1
Timer 2
(5)
Timers
The following timers are incorporated:
Timer 1
16-bit timer
Timer 2
10-bit timer
Timer 3
Watch-dog timer
(6)
FIFO
A 5,120-bit FIFO is incorporated.
Data for one raster is transferred from the RAM
to the FIFO by DMA transmission and is output as serial video data. The data cycle
is 6.13 MHz.