Brother International HL-720 Service Manual - Page 21
<HL-730/730Plus>, Fig. 2.4, Fig. 2.4 shows a block diagram of the main PCB.
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Fig. 2.4 shows a block diagram of the main PCB. Reset Circuit CPU Core (MC68EC000) BUS INT Program + Font ROM 512 Kbytes RAM (0.5 Mbytes) Option RAM (1M or 1.5Mbytes) Option Serial I/O (RS232C & RS422A) EEPROM (128 8 bits) Motor Driver To Panel Sensor PCB Fig. 2.4 A S I C Oscillator (15.3MHz) Address Decoder DRAM Control Timer FIFO DATA EXTENSION CDCC Parallel I/O To PC Soft Support EEPROM I/O Engine Control I/O II-4
II-4
<HL-730/730Plus>
Fig. 2.4 shows a block diagram of the main PCB.
Reset Circuit
Program + Font ROM
512 Kbytes
RAM
(0.5 Mbytes)
Option RAM
(1M or 1.5Mbytes)
Option Serial I/O
(RS232C & RS422A)
EEPROM (128
8 bits)
CPU Core
(MC68EC000)
A
S
I
C
Oscillator (15.3MHz)
Address Decoder
DRAM Control
Timer
FIFO
DATA EXTENSION
CDCC Parallel I/O
Soft Support
EEPROM I/O
Engine Control
I/O
Motor Driver
To Panel Sensor PCB
BUS
INT
To PC
Fig. 2.4