Brother International HL-720 Service Manual - Page 20
Main PCB Block Diagram, <HL-720>, Fig. 2.3, Fig. 2.3 shows a block diagram of the main PCB.
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1.2 Main PCB Block Diagram Fig. 2.3 shows a block diagram of the main PCB. ASIC Reset Circuit CPU Core (Z80) BUS INT DRAM 0.5 Mbytes Option RAM 1.5 Mbytes or 3.5 Mbytes DRAM Control EEPROM (128 x 8 bits) Motor Driver To Panel sensor PCB Fig. 2.3 II-3 Oscillator (12.27 MHz) Program ROM 16 Kbytes Working S-RAM 512 Bytes Timer CDCC Parallel I/O To PC DATA Extension FIFO EEPROM I/O Engine Control I/O
II-3
1.2
Main PCB Block Diagram
<HL-720>
Fig. 2.3 shows a block diagram of the main PCB.
Reset Circuit
DRAM
0.5 Mbytes
Option RAM
1.5 Mbytes or
3.5 Mbytes
EEPROM
(128 x 8 bits)
DRAM Control
Oscillator
(12.27 MHz)
Program ROM
16 Kbytes
Working S-RAM
512 Bytes
Timer
CDCC
Parallel
I/O
DATA
Extension
FIFO
EEPROM
I/O
Engine
Control
I/O
To Panel sensor PCB
To PC
ASIC
CPU Core
(Z80)
BUS
INT
Motor Driver
Fig. 2.3