HP BL25/35/45p HP ProLiant Network Adapter Software and Configuration Guide - Page 26

Counter Test. Clears WG_TO, HB_TO, PA_TO, RT_TO bits by setting those bits. Makes

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• This tests both high and low priorities DMA. It moves data from host memory to adapter SRAM, verifies data, and then moves data back to the host memory again to verify data. • C4. MII test This function is identical to A2. Control Register Test. Each Register specified in the configuration contents is defined as read only bit and read/write bit. The test writes zero and one into the test bits to ensure the read only bits are not changed and read/write bits are changed accordingly. • C5. VPD test The content of VPD is saved first before performing the test. After it is saved, the test writes one of the five pattern test data, 0xff, 0xaa, 0x55, increment data, or decrement data, into VPD memory. By default, increment data pattern is used. It writes and reads back the data for the entire test range, and then it restores the original content. • C6. ASF test The function of this test is as follows: o Reset test. Sets the reset bit and polls for self-clearing. Verifies the reset value of the registers. o Event Mapping Test. Sets SMB_ATTN bit by changing ASF_ATTN LOC bits. Verifies the mapping bits in TX_CPU or RX_CPU event bits. o Counter Test. Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits by setting those bits. Makes sure the bits are clear. Clears the Timestamp Counter. Writes a value 1 into each of the PL, PA, HB, WG, RT counters. Sets the TSC_EN bit. Polls each PA_TO bit and counts up to 50 times. Checks if PL_TO gets set at the end of 50 times. Continues to count up to 200 times. Checks if all other TO bits are set and verifies the Timestamp Counter is incremented. • C7. Expansion ROM test This tests the ability to enable/disable/access the expansion ROM on the device. Group D: Driver associated tests • D1. Mac loopback test This is an internal loopback data transmit/receive test. It initializes MAC into internal loopback mode, and transmits 100 packets. The data should be routed back to the receive channel and is received by the receive routine, which verifies the integrity of data. One Gigabit rate is used for this test. • D2. Phy loopback test This test is the same as D1. Mac Loopback Test except the data is routed back via physical layer device. One Gigabit rate is used for this test. • D5. MII miscellaneous test (copper only) This function tests the auto-polling and phy-interrupt capabilities. These are the functionalities of the phy. • D6. MSI test This tests the Testing Message Interrupt Function to see if it handles this interrupt correctly. The default is disabled. Error codes and messages • Got 0x%08x @ 0x%08x. Expected 0x%08x • Cannot run test while chip is running Configuration and diagnostics 26

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Configuration and diagnostics 26
•
This tests both high and low priorities DMA. It moves data from host memory to adapter SRAM,
verifies data, and then moves data back to the host memory again to verify data.
•
C4. MII test
This function is identical to A2. Control Register Test. Each Register specified in the configuration
contents is defined as read only bit and read/write bit. The test writes zero and one into the test bits
to ensure the read only bits are not changed and read/write bits are changed accordingly.
•
C5. VPD test
The content of VPD is saved first before performing the test. After it is saved, the test writes one of the
five pattern test data, 0xff, 0xaa, 0x55, increment data, or decrement data, into VPD memory. By
default, increment data pattern is used. It writes and reads back the data for the entire test range,
and then it restores the original content.
•
C6. ASF test
The function of this test is as follows:
o
Reset test. Sets the reset bit and polls for self-clearing. Verifies the reset value of the registers.
o
Event Mapping Test. Sets SMB_ATTN bit by changing ASF_ATTN LOC bits. Verifies the mapping
bits in TX_CPU or RX_CPU event bits.
o
Counter Test. Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits by setting those bits. Makes
sure the bits are clear. Clears the Timestamp Counter. Writes a value 1 into each of the PL, PA,
HB, WG, RT counters. Sets the TSC_EN bit. Polls each PA_TO bit and counts up to 50 times.
Checks if PL_TO gets set at the end of 50 times. Continues to count up to 200 times. Checks if all
other TO bits are set and verifies the Timestamp Counter is incremented.
•
C7. Expansion ROM test
This tests the ability to enable/disable/access the expansion ROM on the device.
Group D: Driver associated tests
•
D1. Mac loopback test
This is an internal loopback data transmit/receive test. It initializes MAC into internal loopback
mode, and transmits 100 packets. The data should be routed back to the receive channel and is
received by the receive routine, which verifies the integrity of data. One Gigabit rate is used for this
test.
•
D2. Phy loopback test
This test is the same as D1. Mac Loopback Test except the data is routed back via physical layer
device. One Gigabit rate is used for this test.
•
D5. MII miscellaneous test (copper only)
This function tests the auto-polling and phy-interrupt capabilities. These are the functionalities of the
phy.
•
D6. MSI test
This tests the Testing Message Interrupt Function to see if it handles this interrupt correctly. The default
is disabled.
Error codes and messages
•
Got 0x%08x @ 0x%08x. Expected 0x%08x
•
Cannot run test while chip is running