Oki ML490 Maintenance Manual - Page 15
Rev.1, A/D bus, RAS 1, RAS 0, RAS-N, Clockout, A0~A19, LSICS-N, D0~D7, Write, WRL-N, Address,
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(6) LSI This LSI detects and controls the SP motor speeds by monitoring the two phase sensor signals obtained from the DC motors and modifying the excitation phases as appropriate. This LSI is connected in multiplex to the MPU. MPU LSI A/D bus RD WRL P01 P07 ALE-P RD-N WRL-N LSICS-N ALE ALE RDN WRL LSIC RAS 1 RAS 0 RAS-N Clockout* A0~A19 LSICS-N ALE D0~D7 (Read) RD-N D0~D7 (Write) WRL-N Address Address Data Data * Clockout is provided when the original excitation is selected. 42114101 Rev.1 15 /
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42114101
Rev.1
15 /
(6)
LSI
This LSI detects and controls the SP motor speeds by monitoring the two phase sensor
signals obtained from the DC motors and modifying the excitation phases as appropriate.
This LSI is connected in multiplex to the MPU.
MPU
A/D bus
LSI
RD
WRL
P01
ALE
ALE
RD-N
WRL-N
LSICS-N
ALE-P
RDN
WRL
LSIC
RAS 1
P07
RAS 0
RAS-N
Clockout*
A0~A19
LSICS-N
ALE
D0~D7
(Read)
RD-N
D0~D7
(Write)
WRL-N
Address
Address
Data
Data
* Clockout is provided when the original
excitation is selected.