Dell PowerEdge 4350 Dell PowerEdge 4350 Systems Installation and Troubleshooti - Page 62

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Match case Limit results 1 per page

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100% Actual Size Fit Width Fit Height Fit Page Automatic

5-14

Dell PowerEdge

4350 Systems Installation and Troubleshooting Guide

address´the location of the portion of memory where the error occurred´which

you should record on a copy of the Diagnostics Checklist found in Chapter 12,

²Getting Help.³

²

You receive the

0HPRU\±(&&±IDXOW±GHWHFWHG

message from the Dell

OpenManage Hardware Instrumentation Package (HIP) server management

application program. Refer to the

HP OpenView NNM SE x.x With Dell

OpenManage HIP x.x User±s Guide

for more information about this program.

6\VWHP²6HW²7HVW²*URXS

The subtests in the System Set test group check the computer±s basic system board

components and verify their related functions.

6XEWHVWV

The subtests that constitute the System Set test group and the computer functions

they confirm follow:

²

CMOS Confidence Test

Checks the NVRAM for accessibility and reliability of data storage by performing

a data pattern check and verifying the uniqueness of memory addresses.

²

DMA Controller Test

Tests the direct memory access (DMA) controller and verifies the correct opera-

tion of its page and channel registers by writing patterns to the registers.

²

Real-Time Clock Test

Confirms the functionality and accuracy of the computer±s real-time clock (RTC).

²

System Timers Test

Checks the timers used by the microprocessor for event counting, frequency

generation, and other functions. Only the functions that can be activated by soft-

ware are tested.

²

Interrupt Controller Test

Generates an interrupt on each interrupt request (IRQ) line to verify that devices

using that line can communicate with the microprocessor and that the interrupt

controllers send the correct memory addresses to the microprocessor.

²

APIC Test

Tests that the procedure used to boot a multiprocessor system is able to properly

receive interrupts from the input/output (I/O) Advanced Programmable Interrupt

Controller (APIC).

²

APIC MP Test

Ensures that all microprocessors are able to properly receive interrupts from the

I/O APIC.