Dell PowerEdge R840 EMC Installation and Service Manual - Page 27

Processor Settings details

Page 27 highlights

Processor Settings details About this task The Processor Settings screen details are explained as follows: Option Description Logical Processor Enables or disables the logical processors and displays the number of logical processors. If this option is set to Enabled, the BIOS displays all the logical processors. If this option is set to Disabled, the BIOS displays only one logical processor per core. This option is set to Enabled by default. CPU Interconnect Enables you to govern the frequency of the communication links among the CPUs in the system. Speed NOTE: The standard and basic bin processors support lower link frequencies. The options available are Maximum data rate, 10.4 GT/s, and 9.6 GT/s. This option is set to Maximum data rate by default. Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency that is supported by the processors. You can also select specific frequencies that the processors support, which can vary. For best performance, you should select Maximum data rate. Any reduction in the communication link frequency affects the performance of nonlocal memory accesses and cache coherency traffic. In addition, it can slow access to nonlocal I/O devices from a particular CPU. However, if power-saving considerations outweigh performance, you might want to reduce the frequency of the CPU communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA node to minimize the impact to system performance. Virtualization Technology Enables or disables the virtualization technology for the processor. This option is set to Enabled by default. Adjacent Cache Line Prefetch Optimizes the system for applications that need high utilization of sequential memory access. This option is set to Enabled by default. You can disable this option for applications that need high utilization of random memory access. Hardware Prefetcher Enables or disables the hardware prefetcher. This option is set to Enabled by default. Software Prefetcher Enables or disables the software prefetcher. This option is set to Enabled by default. DCU Streamer Prefetcher Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to Enabled by default. DCU IP Prefetcher Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to Enabled by default. Sub NUMA Cluster Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the LLC. Enables or disables the Sub NUMA Cluster. This option is set to Disabled by default. UPI Prefetch LLC Prefetch Dead Line LLC Alloc Directory AtoS FastGo IRQ Throttle Logical Processor Idling Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path spawns the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to Enabled by default. Enables or disables the LLC Prefetch on all threads. This option is set to Disabled by default. When enabled, it opportunistically fill dead lines in LLC. When disabled, it never fill dead lines in LLC. This option is set to Enabled by default. AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes. This option is set to Disabled by default. Enables you to select CR OOS Configuration Profiles. Enables you to throttle local requests that are targeting a remote address. Enables you to improve the energy efficiency of a system. It uses the operating system core parking algorithm and parks some of the logical processors in the system which in turn allows the corresponding processor cores to Pre-operating system management applications 27

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Processor Settings details
About this task
The
Processor Settings
screen details are explained as follows:
Option
Description
Logical Processor
Enables or disables the logical processors and displays the number of logical processors. If this option is set to
Enabled
, the BIOS displays all the logical processors. If this option is set to
Disabled
, the BIOS displays only one
logical processor per core. This option is set to
Enabled
by default.
CPU Interconnect
Speed
Enables you to govern the frequency of the communication links among the CPUs in the system.
NOTE:
The standard and basic bin processors support lower link frequencies.
The options available are
Maximum data rate
,
10.4 GT/s
, and
9.6 GT/s
. This option is set to
Maximum data
rate
by default.
Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency that is
supported by the processors. You can also select specific frequencies that the processors support, which can
vary.
For best performance, you should select
Maximum data rate
. Any reduction in the communication link frequency
affects the performance of nonlocal memory accesses and cache coherency traffic. In addition, it can slow access
to nonlocal I/O devices from a particular CPU.
However, if power-saving considerations outweigh performance, you might want to reduce the frequency of the
CPU communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA node
to minimize the impact to system performance.
Virtualization
Technology
Enables or disables the virtualization technology for the processor. This option is set to
Enabled
by default.
Adjacent Cache
Line Prefetch
Optimizes the system for applications that need high utilization of sequential memory access. This option is set to
Enabled
by default. You can disable this option for applications that need high utilization of random memory
access.
Hardware
Prefetcher
Enables or disables the hardware prefetcher. This option is set to
Enabled
by default.
Software
Prefetcher
Enables or disables the software prefetcher. This option is set to
Enabled
by default.
DCU Streamer
Prefetcher
Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to
Enabled
by default.
DCU IP Prefetcher
Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to
Enabled
by default.
Sub NUMA Cluster
Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range,
with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the
LLC. Enables or disables the Sub NUMA Cluster. This option is set to
Disabled
by default.
UPI Prefetch
Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path spawns
the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to
Enabled
by
default.
LLC Prefetch
Enables or disables the LLC Prefetch on all threads. This option is set to
Disabled
by default.
Dead Line LLC
Alloc
When enabled, it opportunistically fill dead lines in LLC. When disabled, it never fill dead lines in LLC. This option is
set to
Enabled
by default.
Directory AtoS
AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes. This option
is set to
Disabled
by default.
FastGo
Enables you to select CR OOS Configuration Profiles.
IRQ Throttle
Enables you to throttle local requests that are targeting a remote address.
Logical Processor
Idling
Enables you to improve the energy efficiency of a system. It uses the operating system core parking algorithm and
parks some of the logical processors in the system which in turn allows the corresponding processor cores to
Pre-operating system management applications
27