Intel SPSH4 Product Guide - Page 154

Table 18. Standard BIOS POST Codes (continued) CP Beeps Reason 38 Shadow system BIOS ROM 39 Reinitialize the cache 3A Autosize cache 3C Configure advanced chipset registers 3D Load alternate registers with CMOS values 40 Set Initial Processor speed new 42 Initialize interrupt vectors 44 Initialize BIOS interrupts 46 2-1-2-3 Check ROM copyright notice 47 Initialize manager for PCI Option ROMs 48 Check video configuration against CMOS 49 Initialize PCI bus and devices 4A Initialize all video adapters in system 4B Display QuietBoot screen 4C Shadow video BIOS ROM 4E Display copyright notice 50 Display Processor type and speed 52 Test keyboard 54 Set key click if enabled 55 USB initialization 56 Enable keyboard 58 2-2-3-1 Test for unexpected interrupts 5A Display prompt "Press F2 to enter SETUP" 5C Test RAM between 512 and 640k 60 Test extended memory 62 Test extended memory address lines 64 Jump to UserPatch1 66 Configure advanced cache registers 68 Enable external and processor caches 6A Display external cache size 6B Load custom defaults if required 6C Display shadow message 6E Display non-disposable segments 70 Display error messages 72 Check for configuration errors 74 Test real-time clock 76 Check for keyboard errors 7A Test for key lock on continued 154 Intel SPSH4 Server Platform Product Guide