Intel SR1600UR Service Guide - Page 133
Table 9. Diagnostic LED POST Code Decoder
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Table 9. Diagnostic LED POST Code Decoder Diagnostic LED Decoder O=On; X=Off Checkpoint Upper Nibble MSB Lower Nibble LSB Description 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 0xEDh 0xEEh O OOX O OX O Population Error: RDIMMs and UDIMMs cannot be mixed in the system O O O X O OOX Mismatch Error: more than 2 Quad Ranked DIMMS in a channel. Memory Reference Code Progress Codes (Not accompanied by a beep code) 0xB0h OxB1h 0xB2h 0xB3h 0xB4h OxB6h 0xB8h 0xB9h 0xBAh 0xBBh 0xBFh O X O O X XXX Chipset Initialization Phase O X OOX XXO Reset Phase O X O O X X OX DIMM Detection Phase O X OOX X OO Clock Initialization Phase O X O O X OX X SPD Data Collection Phase O X O O X OOX Rank Formation Phase O X O O O XXX Channel Training Phase O X O O O XXO Memory Test Phase O X O O O X OX Memory Map Creation Phase O X O O O X OO RAS Initialization Phase O X O O O OOO MRC Complete Host Processor 0x04h 0x10h 0x11h 0x12h 0x13h X X X X X OX X Early processor initialization where system BSP is selected X X X O X XXX Power-on initialization of the host processor (bootstrap processor) X X X OX XXO Host processor cache initialization (including AP) X X X O X X OX Starting application processor initialization X X X OX X OO SMM initialization Intel® Server System SR1600UR Service Guide 115