Intel SR1600UR Service Guide - Page 134

Chipset, Memory, Checkpoint, Diagnostic LED Decoder, Description, O=On; X=Off, Upper Nibble, PCI Bus

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Table 9. Diagnostic LED POST Code Decoder Diagnostic LED Decoder O=On; X=Off Checkpoint Upper Nibble MSB Lower Nibble LSB Description 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Chipset 0x21h X X O X X XXO Initializing a chipset component Memory 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h 0x28h X X O X X X OX Reading configuration data from memory (SPD on DIMM) X X O X X X OO Detecting presence of memory X X O X X OX X Programming timing parameters in the memory controller X X O X X OX O Configuring memory parameters in the memory controller X X O X X OOX Optimizing memory controller settings X X O X X OOO Initializing memory, such as ECC init X X O X O XXX Testing memory PCI Bus 0x50h 0x51h 0x52h 0x53h 0x54h 0x55h 0x56h 0x57h X O X O X XXX Enumerating PCI buses X OX OX XXO Allocating resources to PCI buses X O X O X X OX Hot Plug PCI controller initialization X OX OX X OO Reserved for PCI bus X O X O X OX X Reserved for PCI bus X OX OX OX O Reserved for PCI bus X O X O X OOX Reserved for PCI bus X OX OX OOO Reserved for PCI bus USB 0x58h 0x59h X O X O O XXX Resetting USB bus X OX O O XXO Reserved for USB devices 116 Intel® Server System SR1600UR Service Guide

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116
Intel
®
Server System SR1600UR Service Guide
Chipset
0x21h
X
X
O
X
X
X
X
O
Initializing a chipset component
Memory
0x22h
X
X
O
X
X
X
O
X
Reading configuration data from
memory (SPD on DIMM)
0x23h
X
X
O
X
X
X
O
O
Detecting presence of memory
0x24h
X
X
O
X
X
O
X
X
Programming timing parameters in the
memory controller
0x25h
X
X
O
X
X
O
X
O
Configuring memory parameters in the
memory controller
0x26h
X
X
O
X
X
O
O
X
Optimizing memory controller settings
0x27h
X
X
O
X
X
O
O
O
Initializing memory, such as ECC init
0x28h
X
X
O
X
O
X
X
X
Testing memory
PCI Bus
0x50h
X
O
X
O
X
X
X
X
Enumerating PCI buses
0x51h
X
O
X
O
X
X
X
O
Allocating resources to PCI buses
0x52h
X
O
X
O
X
X
O
X
Hot Plug PCI controller initialization
0x53h
X
O
X
O
X
X
O
O
Reserved for PCI bus
0x54h
X
O
X
O
X
O
X
X
Reserved for PCI bus
0x55h
X
O
X
O
X
O
X
O
Reserved for PCI bus
0x56h
X
O
X
O
X
O
O
X
Reserved for PCI bus
0x57h
X
O
X
O
X
O
O
O
Reserved for PCI bus
USB
0x58h
X
O
X
O
O
X
X
X
Resetting USB bus
0x59h
X
O
X
O
O
X
X
O
Reserved for USB devices
Table 9. Diagnostic LED POST Code Decoder
Checkpoint
Diagnostic LED Decoder
Description
O=On; X=Off
Upper Nibble
Lower Nibble
MSB
LSB
8h
4h
2h
1h
8h
4h
2h
1h
LED
#7
#6
#5
#4
#3
#2
#1
#0