Intel E5310 Data Sheet - Page 10

Introduction

10

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Monitor software enabling multiple, independent software environments inside a single

platform. Further details on Intel Virtualization Technology can be found at

http://developer.intel.com/technology/virtualization/index.htm

.

The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance

server and workstation systems. The processors support a Dual Independent Bus (DIB)

architecture with one processor on each bus, up to two processor sockets in a system.

The DIB architecture provides improved performance by allowing increased FSB speeds

and bandwidth. The processors will be packaged in an FC-LGA6 Land Grid Array

package with 771 lands for improved power delivery. It utilizes a surface mount

LGA771 socket that supports Direct Socket Loading (DSL).

Quad-Core Intel® Xeon® Processor 5300 Series based platforms implement

independent core voltage (V

CC

) power planes for each processor. FSB termination

voltage (V

TT

) is shared and must connect to all FSB agents. The processor core voltage

utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load

line (see

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down

(EVRD) 11.0 Design Guidelines

for further details). VRM/EVRD 11.0 will support the

power requirements of all frequencies of the processors including Flexible Motherboard

Guidelines (FMB) (see

Section 2.13.1

). Refer to the appropriate platform design

guidelines for implementation details.

The Quad-Core Intel® Xeon® Processor 5300 Series support either 1333 or 1066 MHz

Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol

and Source-Synchronous Transfer (SST) of address and data to improve performance.

The processor transfers data four times per bus clock (4X data transfer rate, as in AGP

4X). Along with the 4X data bus, the address bus can deliver addresses two times per

bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the

Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X

address bus provide a data bus bandwidth of up to 10.66 GBytes (1333 MHz) or 8.5

GBytes (1066 MHz) per second. The FSB is also used to deliver interrupts.

Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.

Section 2.1

contains the electrical specifications of the FSB while implementation

details are fully described in the appropriate platform design guidelines (refer to

Section 1.3

)

.

Table 1-1.

Quad-Core Intel® Xeon® Processor 5300 Series Features

# of Processor

Cores

L1 Cache (per

core)

L2 Advanced

Transfer Cache

Front Side Bus

Frequency

Package

4

32 KB instruction

32 KB data

4MB Shared L2

Cache per die

8MB Total Cache

1333 MHz

1066 MHz

FC-LGA6

771 Lands

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 10

Table 1-1., Quad-Core Intel® Xeon® Processor 5300 Series Features - lga771

Page 10 highlights