Intel E5310 Data Sheet - Page 66

Table 4-2. Land Listing by Land Number, Sheet 13 of 20, Sheet 14 of 20

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Land Listing Table 4-2. Land Listing by Land Number (Sheet 13 of 20) Pin No. Pin Name F12 F13 F14 F15 F16 F17 F18 F19 F2 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F3 F30 F4 F5 F6 F7 F8 F9 G1 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G2 G20 D24# VSS D28# D30# VSS D37# D38# VSS GTLREF_ADD_MID D41# D43# VSS RESERVED TESTHI07 TESTHI02 TESTHI00 VTT_SEL BCLK0 RESERVED BR0# VTT VSS RS1# RESERVED VSS D17# D18# BPMb0# GTLREF_ADD_END DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# DSTBP2# COMP2 DSTBN2# Signal Buffer Type Direction Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Source Sync Source Sync Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Power/Other Power/Other Power/Other Power/Other Clk Input Input Input Output Input Common Clk Power/Other Power/Other Common Clk Input/Output Input Power/Other Source Sync Source Sync Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Power/Other Source Sync Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Table 4-2. Land Listing by Land Number (Sheet 14 of 20) Pin No. G21 G22 G23 G24 G25 G26 G27 G28 G29 G3 G30 G4 G5 G6 G7 G8 G9 H1 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H2 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H3 Pin Name D44# D47# RESET# TESTHI06 TESTHI03 TESTHI05 TESTHI04 BCLK1 BSEL0 BPMb3# BSEL2 BPMb2# PECI RESERVED DEFER# BPRI# D16# GTLREF_DATA_END VSS VSS VSS VSS VSS DP1# DP2# VSS VSS VSS GTLREF_DATA_MID VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Buffer Type Direction Source Sync Source Sync Common Clk Power/Other Power/Other Power/Other Power/Other Clk Power/Other Common Clk Power/Other Common Clk Power/Other Input/Output Input/Output Input Input Input Input Input Input Output Input/Output Output Output Input/Output Common Clk Common Clk Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/Output Input Input/Output Input/Output Input 66 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

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Land Listing
66
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
F12
D24#
Source Sync
Input/Output
F13
VSS
Power/Other
F14
D28#
Source Sync
Input/Output
F15
D30#
Source Sync
Input/Output
F16
VSS
Power/Other
F17
D37#
Source Sync
Input/Output
F18
D38#
Source Sync
Input/Output
F19
VSS
Power/Other
F2
GTLREF_ADD_MID
Power/Other
Input
F20
D41#
Source Sync
Input/Output
F21
D43#
Source Sync
Input/Output
F22
VSS
Power/Other
F23
RESERVED
F24
TESTHI07
Power/Other
Input
F25
TESTHI02
Power/Other
Input
F26
TESTHI00
Power/Other
Input
F27
VTT_SEL
Power/Other
Output
F28
BCLK0
Clk
Input
F29
RESERVED
F3
BR0#
Common Clk
Input/Output
F30
VTT
Power/Other
F4
VSS
Power/Other
F5
RS1#
Common Clk
Input
F6
RESERVED
F7
VSS
Power/Other
F8
D17#
Source Sync
Input/Output
F9
D18#
Source Sync
Input/Output
G1
BPMb0#
Power/Other
Input/Output
G10
GTLREF_ADD_END
Power/Other
Input
G11
DBI1#
Source Sync
Input/Output
G12
DSTBN1#
Source Sync
Input/Output
G13
D27#
Source Sync
Input/Output
G14
D29#
Source Sync
Input/Output
G15
D31#
Source Sync
Input/Output
G16
D32#
Source Sync
Input/Output
G17
D36#
Source Sync
Input/Output
G18
D35#
Source Sync
Input/Output
G19
DSTBP2#
Source Sync
Input/Output
G2
COMP2
Power/Other
Input
G20
DSTBN2#
Source Sync
Input/Output
Table 4-2. Land Listing by Land Number
(Sheet 13 of 20)
Pin
No.
Pin Name
Signal
Buffer Type
Direction
G21
D44#
Source Sync
Input/Output
G22
D47#
Source Sync
Input/Output
G23
RESET#
Common Clk
Input
G24
TESTHI06
Power/Other
Input
G25
TESTHI03
Power/Other
Input
G26
TESTHI05
Power/Other
Input
G27
TESTHI04
Power/Other
Input
G28
BCLK1
Clk
Input
G29
BSEL0
Power/Other
Output
G3
BPMb3#
Common Clk
Input/Output
G30
BSEL2
Power/Other
Output
G4
BPMb2#
Common Clk
Output
G5
PECI
Power/Other
Input/Output
G6
RESERVED
G7
DEFER#
Common Clk
Input
G8
BPRI#
Common Clk
Input
G9
D16#
Source Sync
Input/Output
H1
GTLREF_DATA_END
Power/Other
Input
H10
VSS
Power/Other
H11
VSS
Power/Other
H12
VSS
Power/Other
H13
VSS
Power/Other
H14
VSS
Power/Other
H15
DP1#
Common Clk
Input/Output
H16
DP2#
Common Clk
Input/Output
H17
VSS
Power/Other
H18
VSS
Power/Other
H19
VSS
Power/Other
H2
GTLREF_DATA_MID
Power/Other
Input
H20
VSS
Power/Other
H21
VSS
Power/Other
H22
VSS
Power/Other
H23
VSS
Power/Other
H24
VSS
Power/Other
H25
VSS
Power/Other
H26
VSS
Power/Other
H27
VSS
Power/Other
H28
VSS
Power/Other
H29
VSS
Power/Other
H3
VSS
Power/Other
Table 4-2. Land Listing by Land Number
(Sheet 14 of 20)
Pin
No.
Pin Name
Signal
Buffer Type
Direction