Intel E5310 Data Sheet - Page 91

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

91

Features

7

Features

7.1

Power-On Configuration Options

Several configuration options can be configured by hardware. Quad-Core Intel® Xeon®

Processor 5300 Series sample its hardware configuration at reset, on the active-to-

inactive transition of RESET#. For specifics on these options, please refer to

Table 7-1

.

The sampled information configures the processor for subsequent operation. These

configuration options cannot be changed except by another reset. All resets reconfigure

the processor, for reset purposes, the processor does not distinguish between a “warm”

reset (PWRGOOD signal remains asserted) and a “power-on” reset.

Notes:

1.

Asserting this signal during RESET# will select the corresponding option.

2.

Address lands not identified in this table as configuration options should not be asserted during RESET#.

3.

Requires de-assertion of PWRGOOD.

Disabling of any of the cores within the Quad-Core Intel® Xeon® Processor 5300

Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).

This MSR will allow for the disabling of a single core per die within the Quad-Core

Intel® Xeon® Processor 5300 Series package. Additional details can be found in the

Intel® 64 and IA-32 Architecture Software Developer’s Manual

.

7.2

Clock Control and Low Power States

Quad-Core Intel® Xeon® Processor 5300 Series support the Extended HALT state (also

referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power

consumption by stopping the clock to internal sections of the processor, depending on

each particular state. See

Figure 7-1

for a visual representation of the processor low

power states. The Extended HALT state is a lower power state than the HALT state or

Stop Grant state.

The Extended HALT state must be enabled via the BIOS for the processor to

remain within its specifications.

Refer to the

Intel® 64 and IA-32 Architecture

Software Developer’s Manual

. For processors that are already running at the lowest bus

to core frequency ratio for its nominal operating point, the processor will transition to

the HALT state instead of the Extended HALT state.

The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In

a multiprocessor system, all the STPCLK# signals are bussed together, thus all

processors are affected in unison. When the STPCLK# signal is asserted, the processor

enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each

processor. The chipset needs to account for a variable number of processors asserting

the Stop Grant SBC on the bus before allowing the processor to be transitioned into one

Table 7-1.

Power-On Configuration Option Lands

Configuration Option

Land Name

Notes

Output tri state

SMI#

1,2,3

Execute BIST (Built-In Self Test)

A3#

1,2

Disable MCERR# observation

A9#

1,2

Disable BINIT# observation

A10#

1,2

Symmetric agent arbitration ID

BR[1:0]#

1,2

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 91

Features, 7.1 Power-On Configuration Options, 7.2 Clock Control and Low Power States

Page 91 highlights