Intel E5310 Data Sheet - Page 86

Thermal Specifications

86

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered

interrupts will be latched and kept pending until the processor resumes operation at the

new frequency.

Once the new operating frequency is engaged, the processor will transition to the new

core operating voltage by issuing a new VID code to the voltage regulator. The voltage

regulator must support dynamic VID steps in order to support Thermal Monitor 2.

During the voltage change, it will be necessary to transition through multiple VID codes

to reach the target operating voltage. Each step will be one VID table entry (see

Table 2-3

). The processor continues to execute instructions during the voltage

transition. Operation at the lower voltage reduces the power consumption of the

processor.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the operating frequency and

voltage transition back to the normal system operating point. Transition of the VID code

will occur first, in order to insure proper operation once the processor reaches its

normal operating frequency. Refer to

Figure 6-4

for an illustration of this ordering.

The PROCHOT# signal is asserted when a high temperature situation is detected,

regardless of whether TM1 or TM2 is enabled.

6.2.4

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption. This mechanism is referred to as “On-

Demand” mode and is distinct from the Thermal Monitor 1 and Thermal Monitor 2

features. On-Demand mode is intended as a means to reduce system level power

consumption. Systems utilizing the Quad-Core Intel® Xeon® Processor 5300 Series

must not rely on software usage of this mechanism to limit the processor temperature.

If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will

immediately reduce its power consumption via modulation (starting and stopping) of

the internal core clock, independent of the processor temperature. When using On-

Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of

the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can

Figure 6-4.

Thermal Monitor 2 Frequency and Voltage Ordering

Vcc

Temperature

Frequency

Time

f

TM2

f

MAX

T

TM2

Vcc

Temperature

V

NOM

Frequency

Time

f

TM2

f

MAX

T

TM2

V

TM2

T(hysterisis)

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 86

On-Demand Mode, Thermal Monitor 2 Frequency and Voltage Ordering

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