Intel E5310 Data Sheet - Page 88

Thermal Specifications

88

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

6.2.7

THERMTRIP# Signal

Regardless of whether or not TM1 or TM2 is enabled, in the event of a catastrophic

cooling failure, the processor will automatically shut down when the silicon has reached

an elevated temperature (refer to the THERMTRIP# definition in

Table 5-1

). At this

point, the FSB signal THERMTRIP# will go active and stay active as described in

Table 5-1

. THERMTRIP# activation is independent of processor activity and does not

generate any bus cycles. Intel also recommends the removal of V

TT

.

6.3

Platform Environment Control Interface (PECI)

6.3.1

Introduction

PECI offers an interface for thermal monitoring of Intel processor and chipset

components. It uses a single wire, thus alleviating routing congestion issues.

Figure 6-5

shows an example of the PECI topology in a system with Quad-Core Intel®

Xeon® Processor 5300 Series. PECI uses CRC checking on the host side to ensure

reliable transfers between the host and client devices. Also, data transfer speeds across

the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI

interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and

must be enabled through BIOS. More information on this can be found in the

Intel® 64

and IA-32 Architecture Software Developer’s Manual

.

6.3.1.1

T

CONTROL

and TCC Activation on PECI-Based Systems

Fan speed control solutions based on PECI utilize a T

CONTROL

value stored in the

processor IA32_TEMPERATURE_TARGET MSR. This MSR uses the same offset

temperature format as PECI, though it contains no sign bit. Thermal management

devices should infer the T

CONTROL

value as negative. Thermal management algorithms

should utilize the relative temperature value delivered over PECI in conjunction with the

MSR value to control or optimize fan speeds.

Figure 6-6

shows a conceptual fan control

diagram using PECI temperatures.

Figure 6-5.

PECI Topology

PECI Host

Controller

Domain0

0

x

3

0

Domain1

0

x

3

0

Domain0

0

x

3

1

Domain1

0

x

3

1

Quad-Core Intel® Xeon®

Processor 5300 Series

(Socket 0)

Quad-Core Intel® Xeon®

Processor 5300 Series

(Socket 1)

G5

G5

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 88

THERMTRIP# Signal, 6.3 Platform Environment Control Interface (PECI), 6.3.1 Introduction

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