Intel E5310 Data Sheet - Page 29

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

29

Electrical Specifications

6.

FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See

Section 2.13.1

for further details on FMB guidelines.

7.

This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END.

8.

V

TT

must be provided via a separate voltage source and must not be connected to V

CC

. This specification is

measured at the land.

9.

Minimum V

CC

and maximum I

CC

are specified at the maximum processor case temperature (T

CASE

) shown

in

Figure 6-1

.

10.

This specification refers to the total reduction of the load line due to VID transitions below the specified

VID.

11.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same

frequency may have different VID settings.

12.

This specification applies to the VCCPLL land.

13.

Baseboard bandwidth is limited to 20 MHz.

14.

I

CC_TDC

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and

should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for

monitoring its temperature and asserting the necessary signal to inform the processor of a thermal

excursion. Please see the applicable design guidelines for further details. The processor is capable of

drawing I

CC_TDC

indefinitely. Refer to

Figure 2-2

and

Figure 2-3

for further details on the average processor

current draw over various time durations. This parameter is based on design characterization and is not

tested.

15.

This is the maximum total current drawn from the V

TT

plane by only one processor with R

TT

enabled. This

specification does not include the current coming from on-board termination (R

TT

), through the signal line.

Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine

the total I

TT

drawn by the system. This parameter is based on design characterization and is not tested.

16.

I

CC

_

VTT

_

OUT

is specified at 1.2 V.

17.

I

CC_RESET

is specified while PWRGOOD and RESET# are asserted.

.

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

CC_TDC

.

2.

Not 100% tested. Specified by design characterization.

Figure 2-2.

Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time

60

65

70

75

80

85

90

95

10 0

0.01

0.1

1

10

10 0

10 0 0

Time Duration (s)

Sustained Current (A)

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 29

Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time, Time Duration s

Page 29 highlights