Intel E5310 Data Sheet - Page 75

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

75

Signal Definitions

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric

error and continue to execute noncontrol floating-point instructions. If IGNNE# is

deasserted, the processor generates an exception on a noncontrol floating-point

instruction if a previous floating-point instruction caused an error. IGNNE# has no

effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

2

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside all processors

without affecting their internal caches or floating-point registers. Each processor then

begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate pins of

all processor FSB agents.

2

LINT[1:0]

I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB agents.

When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a

maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those names on

the Pentium

®

processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC register

space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by

default after Reset, operation of these pins as LINT[1:0] is the default configuration.

2

LL_ID[1:0]

O

The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.

These signals are not connected to the processor die. A logic 0 is pulled to ground and

a logic 1 is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series

package.

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur atomically. This signal

must connect the appropriate pins of all processor FSB agents. For a locked sequence

of transactions, LOCK# is asserted from the beginning of the first transaction to the

end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to

retain ownership of the processor FSB throughout the bus locked operation and

ensure the atomicity of lock.

3

MCERR#

I/O

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable

error without a bus protocol violation. It may be driven by all processor

FSB agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined by the following options:

•

Enabled or disabled.

•

Asserted, if configured, for internal errors along with IERR#.

•

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the

Intel® 64 and

IA-32 Intel® Architecture Software Developer’s Manual, Volume 3: System

Programming Guide

.

MS_ID[1:0]

O

These signals are provided to indicate the Market Segment for the processor and may

be used for future processor compatibility or for keying. These signals are not

connected to the processor die. A logic 0 is pulled to ground and a logic 1 is a no-

connect on the Quad-Core Intel® Xeon® Processor 5300 Series package.

PECI

I/O

PECI is a proprietary one-wire bus interface that provides a communication channel

between Intel processor and chipset components to external thermal monitoring

devices. See

Section 6.3, “Platform Environment Control Interface (PECI)”

for more

on the PECI interface.

PROCHOT#

O

PROCHOT# (Processor Hot) will go active when the processor’s temperature

monitoring sensor detects that the processor has reached its maximum safe operating

temperature. This indicates that the Thermal Control Circuit (TCC) has been

activated, if enabled. The TCC will remain active until shortly after the processor

deasserts PROCHOT#. See

Section 6.2.5

for more details.

Table 5-1.

Signal Definitions (Sheet 5 of 8)

Name

Type

Description

Notes

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 75

Table 5-1., Signal Definitions Sheet 5 of 8

Page 75 highlights