Intel E5310 Data Sheet - Page 24

Electrical Specifications

24

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Note:

1.

Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.

Processors that support these signals will be outlined in the

Quad-Core Intel® Xeon® Processor 5300

Series Specification Update

.

2.8

CMOS Asynchronous and Open Drain

Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,

and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain

signals are required to be asserted/deasserted for at least eight BCLKs in order for the

processor to recognize the proper signal state. See

Section 2.13

for the DC

specifications. See

Section 7

for additional timing requirements for entering and

leaving the low power states.

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Similar considerations must be made for

TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each

driving a different voltage level.

2.10

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel

between Intel processor and external thermal monitoring devices. The Quad-Core

Intel® Xeon® Processor 5300 Series contains Digital Thermal Sensors (DTS)

distributed throughout the die. These sensors are implemented as analog-to-digital

converters calibrated at the factor for reasonable accuracy to provide a digital

representation of relative processor temperature. PECI provides an interface to relay

the highest DTS temperature within a die to external management devices for thermal/

fan speed control.

2.10.1

DC Characteristics

A PECI device interface operates at a nominal voltage set by V

TT

. The set of DC

electrical specifications shown in

Table 2-10

is used with devices normally operating

from a V

TT

interface supply. V

TT

nominal levels will vary between processor families. All

PECI devices will operate at the V

TT

level determined by the processor installed in the

system. For V

TT

specifications, refer to

Table 2-12

.

Table 2-9.

Signal Reference Voltages

GTLREF

CMOS

A[37:3]#

1

, ADS#, ADSTB[1:0]#, AP[1:0]#,

BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#,

BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,

HIT#, HITM#, LOCK#, MCERR#, RESET#,

REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, STPCLK#, TCK, TDI,

TMS, TRST#

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 24

CMOS Asynchronous and Open Drain Asynchronous Signals, 2.9 Test Access Port (TAP) Connection

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