Intel E5310 Data Sheet - Page 89

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

89

Thermal Specifications

6.3.1.2

Processor Thermal Data Sample Rate and Filtering

The DTS provides an improved capability to monitor device hot spots, which inherently

leads to more varying temperature readings over short time intervals. The DTS sample

interval range can be modified, and a data filtering algorithm can be activated to help

moderate this. The DTS sample interval range is 82 ms (default) to 20 ms (max). This

value can be set in BIOS.

To reduce the sample rate requirements on PECI and improve thermal data stability vs.

time the processor DTS also implements an averaging algorithm that filters the

incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed

mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +

(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on

by default and can be turned off in BIOS.

Host controllers should utilize the min/max sample times to determine the appropriate

sample rate based on the controller's fan control algorithm and targeted response rate.

The key items to take into account when settling on a fan control algorithm are the DTS

sample rate, whether the temperature filter is enabled, how often the PECI host will

poll the processor for temperature data, and the rate at which fan speed is changed.

Depending on the designer’s specific requirements the DTS sample rate and alpha-beta

filter may have no effect on the fan control algorithm.

6.3.2

PECI Specifications

6.3.2.1

PECI Device Address

The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that

each address also supports two domains (Domain 0 and Domain 1).

6.3.2.2

PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking

improvements over other compatible industry standard interfaces. The PECI client is as

reliable as the device that it is embedded within, and thus given operating conditions

Figure 6-6.

Conceptual Fan Control Diagram For A PECI-Based Platform

Fan Speed

(RPM)

(not intended to depict actual implementation)

Max

Min

Temperature

PECI = -10

PECI = -20

TCC Activation

Temperature

T

CONTROL

Setting

PECI = 0

Fan Speed

(RPM)

(not intended to depict actual implementation)

Max

Min

Temperature

PECI = -10

PECI = -20

TCC Activation

Temperature

T

CONTROL

Setting

PECI = 0

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 89

PECI Specifications

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