Intel E5310 Data Sheet - Page 50

Land Listing

50

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

ADSTB0#

R6

Source Sync

Input/

Output

ADSTB1#

AD5

Source Sync

Input/

Output

AP0#

U2

Common Clk

Input/

Output

AP1#

U3

Common Clk

Input/

Output

BCLK0

F28

Clk

Input

BCLK1

G28

Clk

Input

BINIT#

AD3

Common Clk

Input/

Output

BNR#

C2

Common Clk

Input/

Output

BPM0#

AJ2

Common Clk

Input/

Output

BPM1#

AJ1

Common Clk

Output

BPM2#

AD2

Common Clk

Output

BPM3#

AG2

Common Clk

Input/

Output

BPM4#

AF2

Common Clk

Output

BPM5#

AG3

Common Clk

Input/

Output

BPMb0#

G1

Common Clk

Input/

Output

BPMb1#

C9

Common Clk

Output

BPMb2#

G4

Common Clk

Output

BPMb3#

G3

Common Clk

Input/

Output

BPRI#

G8

Common Clk

Input

BR0#

F3

Common Clk

Input/

Output

BR1#

H5

Common Clk

Input

BSEL0

G29

Power/Other

Output

BSEL1

H30

Power/Other

Output

BSEL2

G30

Power/Other

Output

COMP0

A13

Power/Other

Input

COMP1

T1

Power/Other

Input

COMP2

G2

Power/Other

Input

COMP3

R1

Power/Other

Input

D00#

B4

Source Sync

Input/

Output

D01#

C5

Source Sync

Input/

Output

D02#

A4

Source Sync

Input/

Output

Table 4-1. Land Listing by Land Name

(Sheet 3 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

D03#

C6

Source Sync

Input/

Output

D04#

A5

Source Sync

Input/

Output

D05#

B6

Source Sync

Input/

Output

D06#

B7

Source Sync

Input/

Output

D07#

A7

Source Sync

Input/

Output

D08#

A10

Source Sync

Input/

Output

D09#

A11

Source Sync

Input/

Output

D10#

B10

Source Sync

Input/

Output

D11#

C11

Source Sync

Input/

Output

D12#

D8

Source Sync

Input/

Output

D13#

B12

Source Sync

Input/

Output

D14#

C12

Source Sync

Input/

Output

D15#

D11

Source Sync

Input/

Output

D16#

G9

Source Sync

Input/

Output

D17#

F8

Source Sync

Input/

Output

D18#

F9

Source Sync

Input/

Output

D19#

E9

Source Sync

Input/

Output

D20#

D7

Source Sync

Input/

Output

D21#

E10

Source Sync

Input/

Output

D22#

D10

Source Sync

Input/

Output

D23#

F11

Source Sync

Input/

Output

D24#

F12

Source Sync

Input/

Output

D25#

D13

Source Sync

Input/

Output

D26#

E13

Source Sync

Input/

Output

D27#

G13

Source Sync

Input/

Output

D28#

F14

Source Sync

Input/

Output

Table 4-1. Land Listing by Land Name

(Sheet 4 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 50

Table 4-1. Land Listing by Land Name, Sheet 3 of 22, Pin Name, Signal, Buffer Type, Direction

Page 50 highlights