Intel E5310 Data Sheet - Page 23

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

23

Electrical Specifications

Notes:

1.

Refer to

Section 5

for signal descriptions.

2.

These signals may be driven simultaneously by multiple agents (Wired-OR).

3.

Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.

Processors that support these signals will be outlined in the

Quad-Core Intel® Xeon® Processor 5300

Series Specification Update

.

Table 2-7

and

Table 2-8

outline the signals which include on-die termination (R

TT

).

Table 2-7

denotes AGTL+ signals, while

Table 2-8

outlines non AGTL+ signals including

open drain signals.

Table 2-9

provides signal reference voltages.

Note:

1.

Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.

Processors that support these signals will be outlined in the

Quad-Core Intel® Xeon® Processor 5300

Series Specification Update

.

Note:

1.

Signals that have a 50

Ω

pullup to V

TT

on package.

CMOS Asynchronous Input

Asynchronous

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK#,

CMOS Asynchronous Output

Asynchronous

BSEL[2:0], VID[6:1]

FSB Clock

Clock

BCLK[1:0]

TAP Input

Synchronous to TCK

TCK, TDI, TMS, TRST#

TAP Output

Synchronous to TCK

TDO

Power/Other

Power/Other

COMP[3:0], GTLREF_ADD_MID,

GTLREF_ADD_END, GTLREF_DATA_MID,

GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0],

PECI, RESERVED, SKTOCC#, TESTHI[11:10],

TESTHI[7:0], TESTIN1, TESTIN2, VCC,

VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL,

VID_SELECT, VSS_DIE_SENSE,

VSS_DIE_SENSE2, VSS, VTT, VTT_OUT,

VTT_SEL

Table 2-6.

FSB Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals

1

Table 2-7.

AGTL+ Signal Description Table

AGTL+ signals with R

TT

AGTL+ signals with no R

TT

A[37:3]#

1

, ADS#, ADSTB[1:0]#, AP[1:0]#,

BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]#

Table 2-8.

Non AGTL+ Signal Description Table

Signals with R

TT

Signals with no R

TT

FORCEPR#

1

, PROCHOT#

1

A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/

PBE#, GTLREF_ADD_MID, GTLREF_ADD_END,

GTLREF_DATA_MID, GTLREF_DATA_END, IERR#,

IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0],

MS_ID[1:0], PECI, PWRGOOD, SKTOCC#, SMI#,

STPCLK#, TCK, TDI, TDO, TESTHI[11:10], TESTHI[7:0],

TESTIN1, TESTIN2, THERMTRIP#, TMS, TRST#,

VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1],

VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2,

VTT_SEL

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 23

Table 2-6., FSB Signal Groups Sheet 2 of 2, AGTL+ Signal Description Table, Signal Group, Signals

Page 23 highlights