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Intel E5310 Data Sheet - Page 25

Input Device Hysteresis, Table 2-10., PECI DC Electrical Limits,

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Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Vin Vhysteresis VN Vp Isource Isink Ileak+ Ileak- Cbus Vnoise Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) High impedance state leakage to VTT (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance per node Signal noise immunity above 300 MHz Min -0.150 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 N/A N/A N/A 0.1 * VTT Max VTT N/A 0.500 * VTT 0.725 * VTT N/A 1.0 50 10 10 N/A Units Notes1 V V V V mA mA µA 2 µA 2 pF 3 Vp-p Note: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 2.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Maximum VN Minimum VN PECI Ground PECI High Range PECI Low Range Minimum Valid Input Hysteresis Signal Range Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 25

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Electrical Specifications

Note:

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

The leakage specification applies to powered devices on the PECI bus.

One node is counted for each client and one node for the system host. Extended trace lengths might appear

as additional nodes.

2.10.2

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use

Figure 2-1

as a guide for input buffer design.

Table 2-10.

PECI DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

Notes

Input Voltage Range

-0.150

hysteresis

Hysteresis

0.1 * V

N/A

Negative-edge threshold

voltage

0.275 * V

0.500 * V

Positive-edge threshold

voltage

0.550 * V

0.725 * V

source

High level output source

= 0.75 * V

)

-6.0

N/A

sink

Low level output sink

= 0.25 * V

)

0.5

1.0

leak+

High impedance state

leakage to V

leak

= V

)

N/A

μA

leak-

High impedance leakage

to GND

leak

= V

)

N/A

μA

bus

Bus capacitance per node

N/A

noise

Signal noise immunity

above 300 MHz

0.1 * V

N/A

p-p

Figure 2-1.

Input Device Hysteresis

Minimum V

Maximum V

Minimum V

Maximum V

PECI High Range

PECI Low Range

Valid Input

Signal Range

Minimum

Hysteresis

PECI Ground