Intel E5310 Data Sheet - Page 77

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

77

Signal Definitions

TESTHI[11:10]

TESTHI[7:0],

I

TESTHI[11:10] and TESTHI[7:0],must be connected to a V

TT

power source through a

resistor for proper processor operation. Refer to

Section 2.6

for TESTHI grouping

restrictions.

TESTIN1

TESTIN2

I

I

TESTIN1 must be connected to a VTT power source through a resistor as well as to

the TESTIN2 land of the same socket for proper processor operation.

TESTIN2 must be connected to a VTT power source through a resistor as well as to

the TESTIN1 land of the same socket for proper processor operation.

Refer to

Section 2.6

for TESTIN restrictions.

THERMTRIP#

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a temperature beyond which permanent silicon damage

may occur. Measurement of the temperature is accomplished through an internal

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal

clocks (thus halting program execution) in an attempt to reduce the processor

junction temperature. To protect the processor its core voltage (V

CC

) must be

removed following the assertion of THERMTRIP#.

Intel also recommends the removal

of V

TT

when THERMTRIP# is asserted.

Driving of the THERMTRIP# signals is enabled within 10

μ

s of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion

of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction

temperature remains at or above the trip level, THERMTRIP# will again be asserted

within 10

μ

s of the assertion of PWRGOOD.

1

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

See the

Debug Port Design Guide for Blackford and Greencreek Systems (External

Version)

for further information.

TRDY#

I

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a

write or implicit writeback data transfer. TRDY# must connect the appropriate pins of

all FSB agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low

during power on Reset.

V

CCPLL

I

The Quad-Core Intel® Xeon® Processor 5300 Series implement an on-die PLL filter

solution. The V

CCPLL

input is used as a PLL supply voltage.

VCC_DIE_SENSE

VCC_DIE_SENSE2

O

VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance

connection to the processor core power and ground. This signal should be connected

to the voltage regulator feedback signal, which insures the output voltage (that is,

processor voltage) remains within specification. Please see the applicable platform

design guide for implementation details.

VID[6:1]

O

VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply

voltages (V

CC

). These are CMOS signals that are driven by the processor and must be

pulled up through a resistor. Conversely, the voltage regulator output must be

disabled prior to the voltage supply for these pins becomes invalid. The VID pins are

needed to support processor voltage specification variations. See

Table 2-3

for

definitions of these pins. The VR must supply the voltage that is requested by these

pins, or disable itself.

VID_SELECT

O

VID_SELECT is an output from the processor which selects the appropriate VID table

for the Voltage Regulator. This signal is not connected to the processor die. This signal

is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series package.

VSS_DIE_SENSE

VSS_DIE_SENSE2

O

VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance

connection to the processor core power and ground. This signal should be connected

to the voltage regulator feedback signal, which insures the output voltage (that is,

processor voltage) remains within specification. Please see the applicable platform

design guide for implementation details.

Table 5-1.

Signal Definitions (Sheet 7 of 8)

Name

Type

Description

Notes

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 77

Table 5-1., Signal Definitions Sheet 7 of 8

Page 77 highlights