Intel E5310 Data Sheet - Page 31

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

31

Electrical Specifications

Notes:

1.

The V

CC_MIN

and V

CC_MAX

loadlines represent static and transient limits. Please see

Section 2.13.2

for VCC

overshoot specifications.

2.

Refer to

Table 2-12

for processor VID information.

3.

Refer to

Table 2-13

for V

CC

Static and Transient Tolerance

4.

The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE

lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage

regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and

VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for

details on VR implementation.

120

VID - 0.150

VID - 0.165

VID - 0.180

1, 2, 3, 4

125

VID - 0.156

VID - 0.171

VID - 0.186

1, 2, 3, 4

Notes:

1.

The V

CC_MIN

and V

CC_MAX

loadlines represent static and transient limits. Please see

Section 2.13.2

for

V

CC

overshoot specifications.

2.

This table is intended to aid in reading discrete points on

Figure 2-4

for Quad-Core Intel® Xeon®

Processor E5300 Series,

Figure 2-5

for Quad-Core Intel® Xeon® Processor X5300 Series.

3.

The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE

lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for

voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE

lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands.

4.

I

cc

value greater than 90 A is not applicable for the Quad-Core Intel® Xeon® Processor E5300 Series.

Figure 2-4.

Quad-Core Intel® Xeon® Processor E5300 Series V

CC

Static and

Transient Tolerance Load Lines

Table 2-13.

V

CC

Static and Transient Tolerance (Sheet 2 of 2)

I

CC

(A)

V

CC_Max

(V)

V

CC_Typ

(V)

V

CC_Min

(V)

Notes

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

VID - 0.100

VID - 0.120

VID - 0.140

VID - 0.160

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

Icc [A]

Vcc [V]

V

CC

Maximum

V

CC

Typical

V

CC

Minimum

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 31

Icc [A], Vcc [V

Page 31 highlights