Intel E5310 Data Sheet - Page 21

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

21

Electrical Specifications

Note:

The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor.

Note:

The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be

used for future processor compatibility or for keying.

2.6

Reserved, Unused, or Test Signals

All Reserved signals must remain unconnected. Connection of these signals to V

CC

, V

TT

,

V

SS

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See

Section 4

for a land listing of the

processor and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active high inputs, should be connected through a

resistor to ground (V

SS

). Unused outputs can be left unconnected; however, this may

interfere with some TAP functions, complicate debug probing, and prevent boundary

scan testing. A resistor must be used when tying bidirectional signals to power or

ground. When tying any signal to power or ground, a resistor will also allow for system

testability. Resistor values should be within ± 20% of the impedance of the baseboard

trace for FSB signals, unless otherwise noticed in the appropriate platform design

guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same

value as the on-die termination resistors (R

TT

). For details see

Table 2-18

.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and utilized outputs must be terminated on the baseboard. Unused

outputs may be terminated on the baseboard or left unconnected. Note that leaving

unused outputs unterminated may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. Signal termination for these signal types

is discussed in the appropriate platform design guidelines.

For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then

terminate the net with a 51

Ω

resistor to V

TT

.

The TESTHI signals must be tied to the processor V

TT

using a matched resistor, where a

matched resistor has a resistance value within ± 20% of the impedance of the board

transmission line traces. For example, if the trace impedance is 50

Ω

, then a value

between 40

Ω

and 60

Ω

is required.

Table 2-4.

Loadline Selection Truth Table for LL_ID[1:0]

LL_ID1

LL_ID0

Description

0

0

Reserved

0

1

Dual-Core Intel® Xeon® Processor 5000 Series


1

0

Reserved

1

1

All Quad-Core Intel® Xeon® Processor 5300 Series

Table 2-5.

Market Segment Selection Truth Table for MS_ID[1:0]

MS_ID1

MS_ID0

Description

0

0


0

1


1

0

All Quad-Core Intel® Xeon® Processor 5300 Series

1

1

Reserved

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 21

Reserved, Unused, or Test Signals, Table 2-4., Loadline Selection Truth Table for LL_ID[1:0]

Page 21 highlights