Intel E5310 Data Sheet - Page 22

Electrical Specifications

22

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

The TESTHI signals may use individual pull-up resistors or be grouped together as

detailed below. A matched resistor must be used for each group:

•

TESTHI[1:0] - can be grouped together with a single pull-up to V

TT

•

TESTHI[7:2] - can be grouped together with a single pull-up to V

TT

•

TESTHI10 – cannot be grouped with other TESTHI signals

•

TESTHI11 – cannot be grouped with other TESTHI signals

2.7

Front Side Bus Signal Groups

The FSB signals have been combined into groups by buffer type. AGTL+ input signals

have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the

term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group

when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as

the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active

anytime and include an active PMOS pull-up transistor to assist during the first clock of

a low-to-high voltage transition.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals whose timings are

specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the

second set is for the source synchronous signals which are relative to their respective

strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals

are still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle.

Table 2-6

identifies which signals are common clock, source synchronous

and asynchronous.

Table 2-6.

FSB Signal Groups (Sheet 1 of 2)

Signal Group

Type

Signals

1

AGTL+ Common Clock Input

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,

TRDY#;

AGTL+ Common Clock Output

Synchronous to

BCLK[1:0]

BPM4#, BPM[2:1]#, BPMb[2:1]#

AGTL+ Common Clock I/O

Synchronous to

BCLK[1:0]

ADS#, AP[1:0]#, BINIT#

2

, BNR#

2

, BPM5#,

BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#,

DBSY#, DP[3:0]#, DRDY#, HIT#

2

, HITM#

2

,

LOCK#, MCERR#

2

AGTL+ Source Synchronous I/O

Synchronous to assoc.

strobe

AGTL+ Strobes I/O

Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Open Drain Output

Asynchronous

FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP#

Signals

Associated Strobe

REQ[4:0]#,A[16:3]#,

A[37:36]#

3

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0#

DSTBP0#, DSTBN0#

D[31:16]#, DBI1#

DSTBP1#, DSTBN1#

D[47:32]#, DBI2#

DSTBP2#, DSTBN2#

D[63:48]#, DBI3#

DSTBP3#, DSTBN3#

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 22

Front Side Bus Signal Groups, Table 2-6., FSB Signal Groups Sheet 1 of 2

Page 22 highlights