Intel E5310 Data Sheet - Page 52

Land Listing

52

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

DSTBP1#

E12

Source Sync

Input/

Output

DSTBP2#

G19

Source Sync

Input/

Output

DSTBP3#

C17

Source Sync

Input/

Output

FERR#/PBE#

R3

ASync GTL+

Output

FORCEPR#

AK6

ASync GTL+

Input

GTLREF_ADD_END

G10

Power/Other

Input

GTLREF_ADD_MID

F2

Power/Other

Input

GTLREF_DATA_END

H1

Power/Other

Input

GTLREF_DATA_MID

H2

Power/Other

Input

HIT#

D4

Common Clk

Input/

Output

HITM#

E4

Common Clk

Input/

Output

IERR#

AB2

ASync GTL+

Output

IGNNE#

N2

ASync GTL+

Input

INIT#

P3

ASync GTL+

Input

LINT0

K1

ASync GTL+

Input

LINT1

L1

ASync GTL+

Input

LL_ID0

V2

Power/Other

Output

LL_ID1

AA2

Power/Other

Output

LOCK#

C3

Common Clk

Input/

Output

MCERR#

AB3

Common Clk

Input/

Output

MS_ID0

W1

Power/Other

Output

MS_ID1

V1

Power/Other

Output

PECI

G5

Power/Other

Input/

Output

PROCHOT#

AL2

ASync GTL+

Output

PWRGOOD

N1

Power/Other

Input

REQ0#

K4

Source Sync

Input/

Output

REQ1#

J5

Source Sync

Input/

Output

REQ2#

M6

Source Sync

Input/

Output

REQ3#

K6

Source Sync

Input/

Output

REQ4#

J6

Source Sync

Input/

Output

RESERVED

A20

RESERVED

A23

RESERVED

A24

Table 4-1. Land Listing by Land Name

(Sheet 7 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

RESERVED

AC4

RESERVED

AE3

RESERVED

AE4

RESERVED

AE6

RESERVED

AH2

RESERVED

AH7

RESERVED

AJ3

RESERVED

AJ7

RESERVED

AK1

RESERVED

AK3

RESERVED

AL1

RESERVED

AM2

RESERVED

AM6

RESERVED

AN5

RESERVED

AN6

RESERVED

B13

RESERVED

B23

RESERVED

C23

RESERVED

D1

RESERVED

D14

RESERVED

D16

RESERVED

E1

RESERVED

E23

RESERVED

E24

RESERVED

E29

RESERVED

E5

RESERVED

E6

RESERVED

E7

RESERVED

F23

RESERVED

F29

RESERVED

F6

RESERVED

G6

RESERVED

J2

RESERVED

J3

RESERVED

N5

RESERVED

T2

RESERVED

Y1

RESERVED

Y3

RESET#

G23

Common Clk

Input

RS0#

B3

Common Clk

Input

Table 4-1. Land Listing by Land Name

(Sheet 8 of 22)

Pin Name

Pin

No.

Signal

Buffer Type

Direction

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 52

Table 4-1. Land Listing by Land Name, Sheet 7 of 22, Sheet 8 of 22

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