Intel E5310 Data Sheet - Page 95
Enhanced Intel SpeedStep® Technology
UPC - 735858190800
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Features 7.2.4.2 7.3 Note: Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS. The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state. While in the Extended HALT Snoop state, snoops and interrupt transactions are handled the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is latched, the processor will return to the Extended HALT state. Enhanced Intel SpeedStep® Technology Quad-Core Intel® Xeon® Processor 5300 Series support Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/frequency states is software controlled. For more configuration details also refer to the Intel® 64 and IA-32 Architecture Software Developer's Manual. Not all Quad-Core Intel® Xeon® Processor 5300 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update when available. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Quad-Core Intel® Xeon® Processor 5300 Series have hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested from the four processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset dependency. - If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. - If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. Refer to the Intel® 64 and IA-32 Architecture Software Developer's Manual for specific information to enable and configure Enhanced Intel SpeedStep Technology in BIOS. § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 95