Intel E5310 Data Sheet - Page 74

Signal Definitions

74

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

3

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

3

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE#

indicates a floating-point error and will be asserted when the processor detects an

unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar

to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility

with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is

asserted, an assertion of FERR#/PBE# indicates that the processor has a pending

break event waiting for service. The assertion of FERR#/PBE# indicates that the

processor should be returned to the Normal state. For additional information on the

pending break event functionality, including the identification of support of the feature

and enable/disable information, refer to Vol. 3 of the

Intel® 64 and IA-32 Intel®

Architecture Software Developer’s Manual

and the

AP-485 Intel® Processor

Identification and the CPUID Instruction

application note.

2

FORCEPR#

I

The FORCEPR# (force power reduction) input can be used by the platform to cause

the Quad-Core Intel® Xeon® Processor 5300 Series to activate the Thermal Control

Circuit (TCC).

GTLREF_ADD_MID

GTLREF_ADD_END

I

GTLREF_ADD determines the signal reference level for AGTL+ address and common

clock input lands. GTLREF_ADD is used by the AGTL+ receivers to determine if a

signal is a logical 0 or a logical 1. Please refer to

Table 2-18

and the appropriate

platform design guidelines for additional details.

GTLREF_DATA_MID

GTLREF_DATA_END

I

GTLREF_DATA determines the signal reference level for AGTL+ data input lands.

GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or

a logical 1. Please refer to

Table 2-18

and the appropriate platform design guidelines

for additional details.

HIT#

HITM#

I/O

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any FSB agent may assert both HIT# and HITM# together to indicate that it

requires a snoop stall, which can be continued by reasserting HIT# and HITM#

together.

3

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor FSB. This transaction may optionally be converted to an external error

signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until

the assertion of RESET#.

This signal does not have on-die termination.

2

Table 5-1.

Signal Definitions (Sheet 4 of 8)

Name

Type

Description

Notes

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBN0#

D[31:16]#, DBI1#

DSTBN1#

D[47:32]#, DBI2#

DSTBN2#

D[63:48]#, DBI3#

DSTBN3#

Signals

Associated Strobes

D[15:0]#, DBI0#

DSTBP0#

D[31:16]#, DBI1#

DSTBP1#

D[47:32]#, DBI2#

DSTBP2#

D[63:48]#, DBI3#

DSTBP3#

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 74

Table 5-1., Signal Definitions Sheet 4 of 8, Description, Notes, Signals, Associated Strobes

Page 74 highlights