Intel E5310 Data Sheet - Page 15

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

15

Electrical Specifications

2

Electrical Specifications

2.1

Front Side Bus and GTLREF

Most Quad-Core Intel® Xeon® Processor 5300 Series FSB signals use Assisted

Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides

improved noise margins and reduced ringing through low voltage swings and controlled

edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the

high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with

the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during

the first clock of a low-to-high voltage transition. Platforms implement a termination

voltage level for AGTL+ signals defined as V

TT

. Because platforms implement separate

power planes for each processor (and chipset), separate V

CC

and V

TT

supplies are

necessary. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address buses have made

signal integrity considerations and platform design methods even more critical than

with previous processor families. Design guidelines for the processor FSB are detailed

in the appropriate platform design guidelines (refer to

Section 1.3

).

The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and

GTLREF_DATA_END are used for the 4X front side bus signaling group and

GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front

side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See

Table 2-18

for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and

GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines

for details. Termination resistors (R

TT

) for AGTL+ signals are provided on the processor

silicon and are terminated to V

TT

. The on-die termination resistors are always enabled

on the processor to control reflections on the transmission line. Intel chipsets also

provide on-die termination, thus eliminating the need to terminate the bus on the

baseboard for most AGTL+ signals.

Some FSB signals do not include on-die termination (R

TT

) and must be terminated on

the baseboard. See

Table 2-7

and

Table 2-8

for details regarding these signals.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for

AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog

signal simulation of the FSB, including trace lengths, is highly recommended when

designing a system. Contact your Intel Field Representative to obtain the applicable

signal integrity models

,

which includes

buffer and package models.

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5310 Data Sheet - Page 15

Electrical Specifications, 2.1 Front Side Bus and GTLREF

Page 15 highlights