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Intel E6700 Mechanical Design Guidelines - Page 62

Critical Parameters for Interfacing to Reference Clip, Critical Core

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ATX Thermal/Mechanical Design Information Figure 6-7. Critical Parameters for Interfacing to Reference Clip Fan Fin Array Core See Detail A Clip Fin Array 1.6 mm Clip Core Detail A Figure 6-8. Critical Core Dimension 1.00 +/- 0.10 mm 1.00 mm min Φ38.68 +/- 0.30 mm Φ36.14 +/- 0.10 mm Gap required to avoid core surface blemish during clip assembly. Recommend 0.3 mm min. Core R 0.40 mm max R 0.40 mm max 2.596 +/- 0.10 mm NOTE: Dimension from the bottom of the clip to the bottom of the heatsink core (or base) should be met to enable the required load from the heatsink clip (i.e., 43 lbf nominal +/- 10 lbf) § 62 Thermal and Mechanical Design Guidelines

Section	Page
1 Introduction	9
1.1 Document Goals and Scope	9
1.1.1 Importance of Thermal Management	9
1.1.2 Document Goals	9
1.1.3 Document Scope	10
1.2 References	11
1.3 Definition of Terms	11
2 Processor Thermal/Mechanical Information	13
2.1 Mechanical Requirements	13
2.1.1 Processor Package	13
2.1.2 Heatsink Attach	15
2.1.2.1 General Guidelines	15
2.1.2.2 Heatsink Clip Load Requirement	15
2.1.2.3 Additional Guidelines	16
2.2 Thermal Requirements	16
2.2.1 Processor Case Temperature	16
2.2.2 Thermal Profile	17
2.2.3 Thermal Solution Design Requirements	17
2.2.4 TCONTROL	18
2.3 Heatsink Design Considerations	19
2.3.1 Heatsink Size	20
2.3.2 Heatsink Mass	20
2.3.3 Package IHS Flatness	21
2.3.4 Thermal Interface Material	21
2.4 System Thermal Solution Considerations	22
2.4.1 Chassis Thermal Design Capabilities	22
2.4.2 Improving Chassis Thermal Performance	22
2.4.3 Summary	23
2.5 System Integration Considerations	23
3 Thermal Metrology	25
3.1 Characterizing Cooling Performance Requirements	25
3.1.1 Example	26
3.2 Processor Thermal Solution Performance Assessment	27
3.3 Local Ambient Temperature Measurement Guidelines	27
3.4 Processor Case Temperature Measurement Guidelines	30
4 Thermal Management Logic and Thermal Monitor Feature	31
4.1 Processor Power Dissipation	31
4.2 Thermal Monitor Implementation	31
4.2.1 PROCHOT# Signal	32
4.2.2 Thermal Control Circuit	32
4.2.2.1 Thermal Monitor	32
4.2.3 Thermal Monitor 2	33
4.2.4 Operation and Configuration	34
4.2.5 On-Demand Mode	35
4.2.6 System Considerations	35
4.2.7 Operating System and Application Software Considerations	36
4.2.8 THERMTRIP# Signal	36
4.2.9 Cooling System Failure Warning	36
4.2.10 Digital Thermal Sensor	37
4.2.11 Platform Environmental Control Interface (PECI)	38
5 Balanced Technology Extended (BTX) Thermal/Mechanical Design Information	39
5.1 Overview of the BTX Reference Design	39
5.1.1 Target Heatsink Performance	39
5.1.2 Acoustics	40
5.1.3 Effective Fan Curve	41
5.1.4 Voltage Regulator Thermal Management	42
5.1.5 Altitude	43
5.1.6 Reference Heatsink Thermal Validation	43
5.2 Environmental Reliability Testing	43
5.2.1 Structural Reliability Testing	43
5.2.1.1 Random Vibration Test Procedure	43
5.2.1.2 Shock Test Procedure	44
5.2.2 Power Cycling	45
5.2.3 Recommended BIOS/CPU/Memory Test Procedures	46
5.3 Material and Recycling Requirements	46
5.4 Safety Requirements	47
5.5 Geometric Envelope for Intel® Reference BTX Thermal Module Assembly	47
5.6 Preload and TMA Stiffness	48
5.6.1 Structural Design Strategy	48
5.6.2 TMA Preload verse Stiffness	48
6 ATX Thermal/Mechanical Design Information	51
6.1 ATX Reference Design Requirements	51
6.2 Validation Results for Reference Design	53
6.2.1 Heatsink Performance	53
6.2.2 Acoustics	54
6.2.3 Altitude	54
6.2.4 Heatsink Thermal Validation	55
6.3 Environmental Reliability Testing	55
6.3.1 Structural Reliability Testing	55
6.3.1.1 Random Vibration Test Procedure	55
6.3.1.2 Shock Test Procedure	56
6.3.2 Power Cycling	57
6.3.3 Recommended BIOS/CPU/Memory Test Procedures	58
6.4 Material and Recycling Requirements	58
6.5 Safety Requirements	59
6.6 Geometric Envelope for Intel® Reference ATX Thermal Mechanical Design	59
6.7 Reference Attach Mechanism	60
6.7.1 Structural Design Strategy	60
6.7.2 Mechanical Interface to the Reference Attach Mechanism	61
7 Intel® Quiet System Technology (Intel® QST)	63
7.1 Intel® QST Algorithm	63
7.1.1 Output Weighting Matrix	64
7.1.2 Proportional-Integral-Derivative (PID)	64
7.2 Board and System Implementation of Intel® QST	66
7.3 Intel® QST Configuration and Tuning	68