Intel E6700 Mechanical Design Guidelines - Page 66
Board and System Implementation of Intel - 2 66
UPC - 735858184618
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Intel® Quiet System Technology (Intel® QST) 7.2 Board and System Implementation of Intel® QST To implement Intel QST, the board must be configured as shown in Figure 7-3 and listed below: • ME system (S0-S1) with Controller Link connected and powered • DRAM with Channel A DIMM 0 installed and 2 MB reserved for Intel QST FW execution • SPI Flash with sufficient space for the Intel QST Firmware • SST-based thermal sensors to provide board thermal data for Intel QST algorithms • Intel QST firmware Figure 7-3. Intel® QST Platform Requirements Processor Intel® (G)MCH MMEE DRAM DRAM Intel® ICH8 Controller Link FSC Control SPI SPI Flash SST Sensor Note: Simple Serial Transport (SST) is a single wire bus that is included in the ICH8 to provide additional thermal and voltage sensing capability to the Intel Management Engine (ME). 66 Thermal and Mechanical Design Guidelines