Intel BB5520UR Product Specification - Page 147

Capacitive Loading, Ripple/Noise, Timing Requirements

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Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Design and Environmental Specifications Table 76. Transient Load Requirements Output Δ Step Load Size 1 Load Slew Rate Test Capacitive Load +3.3 V 7.0 A 0.25A/μsec 4700μF +5 V 7.0 A 0.25A/μsec 1000μF +12 V 25 A 0.25A/μsec 4700μF +5 VSB 0.5 A 0.25A/μsec 20μF 1. Step loads on each 12 V output may happen simultaneously. 9.4.6 Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range. Table 77. Capacitive Loading Conditions Output +3.3V +5V +12V1, +12V2, +12V3, +12V4 -12V +5VSB Minimum 250 400 500 each 1 20 Maximum 6800 4700 11,000 350 350 Units μF μF μF μF μF 9.4.7 Ripple/Noise The maximum allowed ripple/noise output of the power supply is defined in the following table. This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor are placed at the point of measurement. Table 78. Ripple and Noise +3.3V +5V +12V1, +12V2, +12V3, +12V4 -12V +5 VSB 50 mVp-p 50 mVp-p 120 mVp-p 120 mVp-p 50 mVp-p 9.4.8 Timing Requirements The following are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 ms to 70 ms. 5 VSB is allowed to rise from 1.0 ms to 25 ms. +3.3 V, +5 V, and +12 V output voltages should start to rise approximately at the same time. All outputs must rise monotonically. Each output voltage should reach regulation within 50 ms (Tvout_on) of each other during turn on of the power supply. Each output voltage should fall out of regulation within 400 msec (Tvout_off) of each other during turn off. The following tables and diagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low, and the PSON signal with the AC input applied. Revision 1.8 133 Intel order number E39529-013

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Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS
Design and Environmental Specifications
Revision 1.8
Intel order number E39529-013
133
Table 76. Transient Load Requirements
Output
Δ
Step Load Size 1
Load Slew Rate
Test Capacitive Load
+3.3 V
7.0 A
0.25A/
μ
sec
4700
μ
F
+5 V
7.0 A
0.25A/
μ
sec
1000
μ
F
+12 V
25 A
0.25A/
μ
sec
4700
μ
F
+5 VSB
0.5 A
0.25A/
μ
sec
20
μ
F
1.
Step loads on each 12 V output may happen simultaneously.
9.4.6
Capacitive Loading
The power supply should be stable and meet all requirements within the following capacitive
loading range.
Table 77. Capacitive Loading Conditions
Output
Minimum
Maximum
Units
+3.3V
250
6800
μ
F
+5V
400
4700
μ
F
+12V1, +12V2, +12V3, +12V4
500 each
11,000
μ
F
-12V
1
350
μ
F
+5VSB
20
350
μ
F
9.4.7
Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A
10
μ
F tantalum capacitor in parallel with a 0.1
μ
F ceramic capacitor are placed at the point of
measurement.
Table 78. Ripple and Noise
+3.3V
+5V
+12V1, +12V2, +12V3, +12V4
-12V
+5 VSB
50 mVp-p
50 mVp-p
120 mVp-p
120 mVp-p
50 mVp-p
9.4.8
Timing Requirements
The following are the timing requirements for the power supply operation. The output voltages
must rise from 10% to within regulation limits (T
vout_rise
) within 5 ms to 70 ms. 5 VSB is allowed to
rise from 1.0 ms to 25 ms. +3.3 V, +5 V, and +12 V output voltages should start to rise
approximately at the same time. All outputs must rise monotonically. Each output voltage should
reach regulation within 50 ms (T
vout_on
) of each other during turn on of the power supply. Each
output voltage should fall out of regulation within 400 msec (T
vout_off
) of each other during turn off.
The following tables and diagrams show the timing requirements for the power supply being
turned on and off via the AC input with PSON held low, and the PSON signal with the AC input
applied.