Intel BB5520UR Product Specification - Page 52

Memory Error Handling

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Functional Architecture Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.3.11 Memory Error Handling The BIOS classifies memory errors into the following categories: ƒ Correctable ECC errors: This correction could be the result of an ECC correction, a successfully retried memory cycle, or both. ƒ Unrecoverable/Fatal ECC Errors: The ECC engine detects these errors but cannot correct them. ƒ Address Parity Errors: An Address Parity Error is logged as such in the SEL, but in all other ways, is treated the same as an Uncorrectable ECC Error. 38 Revision 1.8 Intel order number E39529-013

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Functional Architecture
Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS
Revision 1.8
Intel order number E39529-013
38
3.3.11
Memory Error Handling
The BIOS classifies memory errors into the following categories:
±
Correctable ECC errors
: This correction could be the result of an ECC correction, a
successfully retried memory cycle, or both.
±
Unrecoverable/Fatal ECC Errors
: The ECC engine detects these errors but cannot
correct them.
±
Address Parity Errors
: An Address Parity Error is logged as such in the SEL, but in all
other ways, is treated the same as an Uncorrectable ECC Error.