Intel BB5520UR Product Specification - Page 186

Glossary Term ACPI AHCI AMT AP APIC ARP ASIC ATS BBS BEV BIOS BIST BMC bpp bps BSP Byte CL CLTT CMOS DCA DDR3 DHCP DIMM DMA DPC DXE ECC EEPROM EFUP EHCI EIST EMC EMP EPS ESI EVRD FMB FRB FRU FW FWH GB 172 Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Glossary Definition Advanced Configuration and Power Interface Advanced Host Controller Interface Active Management Technology Application Processor Advanced Programmable Interrupt Control Address Resolution Protocol Application Specific Integrated Circuit Address Translation Technology BIOS Boot Specification Boot Entry Vector Basic Input/Output System Built-in Self Test Baseboard Management Controller Bits per pixel bit per second Boot Strap Processor 8-bit quantity Controller Link Closed-Loop Thermal Throttling In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. Direct Cache Access Double Data Rate 3 Dynamic Host Configuration Protocol Dual in-line memory module Direct Memory Access Direct Platform Control Driver eXecution Environment Error Correction Code Electrically Erasable Programmable Read-Only Memory Environment Friendly Usage Period Enhanced Host Controller Interface Enhanced Intel SpeedStep® Technology Electromagnetic Compatibility Emergency Management Port External Product Specification Enterprise South Bridge Interface Enterprise Voltage Regulator-Down Flexible Mother Board Fault Resilient Boot Field Replaceable Unit Firmware Firmware Hub 1024 MB Intel order number E39529-013 Revision 1.8