Intel BB5520UR Product Specification - Page 49

Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture • Optimization techniques used by the Intel® Xeon® Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode, all the DDR3 channels operate independently. Also, you can use the Independent Channel mode to support single DIMM configuration in Channel A and in the Single Channel mode. You must observe and apply the following general rules when selecting and configuring memory to obtain the best performance from the system: 1. Mixing RDIMMs and UDIMMs is not supported. 2. You must populate CPU1 socket first in order to enable and operate CPU2 socket. 3. When CPU2 socket is empty, DIMMs populated in slots D1 through F2 are unusable. 4. If both CPU sockets are populated, but Channels A through C are empty, the platform can still function with remote memory in Channels D through F. However, platform performance suffers latency due to remote memory. 5. Must always start populating DDR3 DIMMs in the first slot on each memory channel (Memory slot A1, B1, C1, D1, E1, or F1). For example, if memory slot A1 is empty, slot A2 is not available. 6. Must always populate the Quad-Rank DIMM starting with the first slot (Memory slot A1, B1, C1, D1, E1, or F1) on each memory channel. For example, when installing one Quad-Rank RDIMM with one Single- or Dual-Rank RDIMM in memory channel A, you must populate the Quad-Rank RDIMM in slot A1. 7. If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during memory initialization and is (essentially) disabled by the BIOS. If a DDR3 DIMM has no or missing SPD information, the slot in which it is placed is treated as empty by the BIOS. 8. The memory operational mode is configurable at the channel level. The following two modes are supported: Independent Channel Mode and Mirrored Channel Mode. 9. The BIOS selects the mode that enables all the installed memory by default. Since the Independent Channel Mode enables all the channels simultaneously, this mode becomes the default mode of operation. 10. When only CPU1 socket is populated, Mirrored Channel mode is selected only if the DIMMs are populated to conform to that channel RAS mode. If it fails to comply with the population rule, then the BIOS configures the CPU1 socket to default to the Independent Channel mode. 11. If both CPU sockets are populated and the installed DIMMs are associated with both CPU sockets, then Mirrored Channel Mode can only be selected if both the CPU sockets are populated to conform to that mode. If either or both sockets fail to comply with the population rule, the BIOS configures both the CPU sockets to default to the Independent Channel mode. 12. DIMM parameters matching requirements for Mirrored Channel Mode is local to the CPU socket. For example, while CPU1 memory channels A, B, and C have one match of timing, technology and size, CPU 2 memory channels D, E, and F can have a different match of the parameters, channel RAS still functions. 13. The Minimal memory population possible is DIMM_A1. In this configuration, the system operates in the Independent Channel Mode. Mirrored Channel Mode is not possible. Revision 1.8 35 Intel order number E39529-013