Intel BB5520UR Product Specification - Page 39

Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture z Intel® 64 mode when 64-bit extension technology is enabled (Entering Intel® 64 mode requires enabling PAE). You can enable and disable the XD bit in the BIOS Setup. The default behavior is enabled. 3.2.7 Core Multi-Processing The BIOS setup provides the ability to selectively enable one or more cores. The default behavior is to enable all cores. You can do this through the BIOS setup option for active core count. The BIOS creates entries in the Multi-Processor Specification, Version 1.4 tables to describe multi-core processors. 3.2.8 Direct Cache Access (DCA) Direct Cache Access (DCA) is a system-level protocol in a multi-processor system to improve I/O network performance, thereby providing higher system performance. The basic idea is to minimize cache misses when a demand read is executed. This is accomplished by placing the data from the I/O devices directly into the processor cache through hints to the processor to perform a data pre-fetch and install it in its local caches. The BIOS setup provides an option to enable or disable this feature. The default behavior is enabled. 3.2.9 Unified Retention System Support The server boards comply with Unified Retention System (URS) and Unified Backplate Assembly. The server boards ship with Unified Backplate Assembly at each processor socket. The URS retention transfers load to the server boards via the Unified Backplate Assembly. The URS spring, captive in the heatsink, provides the necessary compressive load for the thermal interface material (TIM). All components of the URS heatsink solution are captive to the heatsink and only require a Phillips* screwdriver to attach to the Unified Backplate Assembly. See the following figure for the stacking order of URS components. The Unified Backplate Assembly is removable, allowing for the use of non-Intel® heatsink retention solutions. Revision 1.8 25 Intel order number E39529-013