Intel BB5520UR Product Specification - Page 41

Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture 3.3 Memory Subsystem The Intel® Xeon® Processor 5500 Series on the Intel® Server Boards S5520HC, S5500HCV and S5520HCT are populated on CPU sockets. Each processor installed on the CPU socket has an integrated memory controller (IMC), which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory. 3.3.1 Memory Subsystem Nomenclature The nomenclature for DIMM sockets implemented in the Intel® Server Boards S5520HC, S5500HCV and S5520HCT is represented in the following figures. z DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets. z The memory channels for CPU 1 socket are identified as Channels A, B, and C. The memory channels for CPU 2 socket are identified as Channels D, E, and F. z The DIMM identifiers on the silkscreen on the board provide information about which channel/CPU Socket they belong to. For example, DIMM_A1 is the first slot on Channel A of CPU 1 socket. DIMM_D1 is the first slot on Channel D of CPU 2 Socket. z Processor sockets are self-contained and autonomous. However, all configurations in the BIOS setup, such as RAS, Error Management, and so forth, are applied commonly across sockets. The Intel® Server Board S5520HC supports six DDR3 memory channels (three channels per processor) with two DIMM slots per channel, thus supporting up to twelve DIMMs in twoprocessor configuration. See Figure 16 for the Intel® Server Board S5520HC DIMM slots arrangement. The Intel® Server Board S5500HCV supports six DDR3 memory channels (three channels per processor) with two DIMM slots per channel at Channels A, B, and C, and one DIMM slot per channel at Channels D, E, and F, thereby supporting up to nine DIMMs in a two-processor configuration. See Figure 17 for the Intel® Server Board S5500HCV DIMM slots arrangement. Revision 1.8 27 Intel order number E39529-013