Intel BB5520UR Product Specification - Page 47

Memory Test, Memory Scrub Engine, Memory RAS

Get Intel BB5520UR PDF manuals and user guides View all Intel BB5520UR manuals
Add to My Manuals
Save this manual to your list of manuals

Page 47 highlights

Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture • Bank Interleaving - Interleave cache-line data between participant ranks. • Channel Interleaving - Interleave between channel when not in Mirrored Channel Mode. • Socket Interleaving - Interleaved memory can spread between both CPU sockets when NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are installed in slots for both sockets. 3.3.6 Memory Test 3.3.6.1 Integrated Memory BIST Engine The Intel® Xeon® Processor 5500 series incorporate an integrated Memory Built-in Self Test (BIST) engine enabled to provide extensive coverage of memory errors at both the memory cells and the data paths emanating from the DDR3 DIMMs. The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery process. 3.3.7 Memory Scrub Engine The Intel® Xeon® Processor 5500 Series incorporates a memory scrub engine, which performs periodic checks on the memory cells, and identifies and corrects single-bit errors. Two types of scrubbing operations are supported: • Demand scrubbing - Executes when an error is encountered during normal read/write of data. • Patrol scrubbing - Proactively walks through populated memory space seeking soft errors. The BIOS enables both demand scrubbing and patrol scrubbing by default. Demand scrubbing is not possible when memory mirroring is enabled. Therefore, if the memory is configured for mirroring, the BIOS disables it automatically. 3.3.8 Memory RAS 3.3.8.1 RAS Features The Intel® Server Boards S5520HC, S5500HCV and S5520HCT support the following memory channel modes: • Independent Channel Mode • Mirrored Channel Mode - providing Channel RAS feature These channel modes are used in conjunction with the standard Memory Test (Built-in Self-Test (BIST) and Memory Scrub engines to provide full RAS support. Channel RAS feature are supported only if both CPU sockets are populated and support the right population. For more information, refer to Section 3.3.9. Revision 1.8 33 Intel order number E39529-013

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS
Functional Architecture
Revision 1.8
Intel order number E39529-013
33
•
Bank Interleaving – Interleave cache-line data between participant ranks.
•
Channel Interleaving – Interleave between channel when not in Mirrored Channel Mode.
•
Socket Interleaving – Interleaved memory can spread between both CPU sockets when
NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are
installed in slots for both sockets.
3.3.6
Memory Test
3.3.6.1
Integrated Memory BIST Engine
The Intel
®
Xeon
®
Processor 5500 series incorporate an integrated Memory Built-in Self Test
(BIST) engine enabled to provide extensive coverage of memory errors at both the memory
cells and the data paths emanating from the DDR3 DIMMs.
The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery
process.
3.3.7
Memory Scrub Engine
The Intel
®
Xeon
®
Processor 5500 Series incorporates a memory scrub engine, which performs
periodic checks on the memory cells, and identifies and corrects single-bit errors. Two types of
scrubbing operations are supported:
•
Demand scrubbing
– Executes when an error is encountered during normal read/write
of data.
•
Patrol scrubbing
– Proactively walks through populated memory space seeking soft
errors.
The BIOS enables both demand scrubbing and patrol scrubbing by default.
Demand scrubbing is not possible when memory mirroring is enabled. Therefore, if the memory
is configured for mirroring, the BIOS disables it automatically.
3.3.8
Memory RAS
3.3.8.1
RAS Features
The Intel
®
Server Boards S5520HC, S5500HCV and S5520HCT support the following memory
channel modes:
•
Independent Channel Mode
•
Mirrored Channel Mode – providing Channel RAS feature
These channel modes are used in conjunction with the standard Memory Test (Built-in Self-Test
(BIST) and Memory Scrub engines to provide full RAS support.
Channel RAS feature are supported only if both CPU sockets are populated and support the
right population. For more information, refer to Section 3.3.9.