Intel BB5520UR Product Specification - Page 51
Table 5. Supported DIMM Population under the Dual Processors Configuration, Table 6. Supported DIMM
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Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Table 5. Supported DIMM Population under the Dual Processors Configuration # N CPU1 Socket = Populated CPU2 Socket = Populated A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 M 1 1 X N 2 2 X X N 3 2 X X N 4 2 X X N 5 3 X X X N 6 3 X X X N 7 3 X X X N 8 4 X X X X N 9 4 X X X X Y 10 6 X X X X X X Y 11 6 X X X X X X N 12 7 X X X X X X X N 13 8 X X X X X X X X Y 14 8 X X X X X X X X N 15 9 X X X X X X X X X N 16 12 X X X X X X X X X X X X N Table 6. Supported DIMM Population under the Single Processor Configuration # N CPU1 Socket = Populated CPU2 Socket = Empty A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 M 1 1 X N 2 2 X X N 3 2 X X Y 4 3 X X X N 5 4 X X X X N 6 4 X X X X Y 7 6 X X X X X X N Note: The generic principles and guidelines described in the above sections also apply to the above two tables. Revision 1.8 37 Intel order number E39529-013