HP Integrity Superdome SX1000 User Guide, Sixth Edition - HP Integrity Superdo - Page 23

Figure 1-6 Cell Board Functional Block Diagram Overview Cell Board Cell Controller The CC has five major interfaces: • Processor (two independent FSBs) • Crossbar (cell interconnect fabric) • Remote I/O link • Memory subsystem • Platform-dependant hardware (PDH) Using an internal, centralized data path, the CC maintains cache coherency throughout the system with memory tags. It also has an internal PLL that helps simplify clock distribution within the confines of the ASIC and source additional clocks to the memory and PDH subsystems. Processors and Front-Side Bus Interfaces Each of the two FSBs is connected to two processor modules in a standard three-drop FSB configuration. The CC minimizes total routing delay without sacrificing timing skew between the FSB address and data and control signals to achieve a frequency of 200 MHz transmitting data on both edges of the interface clock. With the 128-bit FSB capable of achieving 400 MT/s, a 6.4 MB/s burst data transfer rate can be realized. Crossbar Link The crossbar link is a self-correcting, high-speed interface between the CC and the crossbar backplane. It comprises eight data "bundles," each with a differential strobe for synchronization, designed to achieve a peak data transfer rate of 2 GB/s. Four of the eight bundles are used for input data, and each bundle contains Chapter 1 11