Intel SR2600UR Service Guide - Page 179
Table 8. Diagnostic LED POST Code Decoder - chipset
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Table 8. Diagnostic LED POST Code Decoder Diagnostic LED Decoder O=On; X=Off Checkpoint Upper Nibble MSB Lower Nibble LSB Description 8h 4h 2h 1h 8h 4h 2h 1h LED 0xEDh 0xEEh #7 #6 #5 #4 #3 #2 #1 #0 O OOX O OX O Population Error: RDIMMs and UDIMMs cannot be mixed in the system O O O X O OOX Mismatch Error: more than 2 Quad Ranked DIMMS in a channel. Memory Reference Code Progress Codes (Not accompanied by a beep code) 0xB0h O X O O X XXX Chipset Initialization Phase OxB1h O X OOX XXO Reset Phase 0xB2h O X O O X X OX DIMM Detection Phase 0xB3h O X OOX X OO Clock Initialization Phase 0xB4h O X O O X OX X SPD Data Collection Phase OxB6h O X O O X OOX Rank Formation Phase 0xB8h O X O O O XXX Channel Training Phase 0xB9h O X O O O XXO Memory Test Phase 0xBAh O X O O O X OX Memory Map Creation Phase 0xBBh O X O O O X OO RAS Initialization Phase 0xBFh O X O O O OOO MRC Complete Host Processor 0x04h X 0x10h X 0x11h X 0x12h X 0x13h X X X X X OX X Early processor initialization where system BSP is selected X X O X XXX Power-on initialization of the host processor (bootstrap processor) X X OX XXO Host processor cache initialization (including AP) X X O X X OX Starting application processor initialization X X OX X OO SMM initialization Intel® Server System SR2600UR/SR2625UR Service Guide 159