Toshiba Tecra A2-S239 Maintenance Manual - Page 22

1 Hardware Overview 1.2 System Block Diagram q Chipset This gate array has the following elements and functions. • North Bridge (Intel Montara-GML or Intel Montara-GM+) − CPU interface and controller − Host bus support − System memory SDRAM controller − Hub interface − AGP interface − Power management − Graphic controller • South Bridge (Intel ICH4-M) − LAN controller − IDE controller − DMA controller − USB interface − SM Bus interface − Interrupt controller − Power management − Firmware Hub interface − Low Pin count (LPC) interface − Real time clock − AC'97 interface − Audio controller − Hub interface q PC card controller (YEBISUSS) − PCI interface (PCI Revision 2.2) − Deeper Sleep control interface − Chipset interface Intel serial interrupt − Card Bus /PC card controller (Yenta Version 2.2: 1 slot) Parallel power control (Toshiba style) − SD memory card controller (SDHC Version 1.2) − SD IO card controller (Version 1.1) − Smart Card interface debug port − Docking station interface Q Switch control, reset control − External device interface FDD/IDE hot plug plug-and-play control 1-8 Satellite A50/TECRA A2 Maintenance Manual (960-478)