Toshiba Tecra A2-S239 Maintenance Manual - Page 77

2.4 System Board Troubleshooting 2 Troubleshooting Procedures D port status F100h F101h F102h F103h Table 2-3 D port status (3/9) Inspection items Details Disabling cache Initializing H/W (before recognizing DRAM) Initializing MCHM Initializing ICH4M.D31.Func0 Initializing ICH4M.D31.Func1 Initializing USB.Func0,1,2,7 Initializing ICH4M.D31.Func3 Initializing ICH4M.D31.Func5 Initializing FLUTE Initializing the channel 1 of a PIT (set 30 µs for refresh interval) Checking type and size of DRAM (at Cold boot only) HLT when DRAM size is 0 Testing stack area of SM-RAM HLT when impossible to use as s tack CMOS check and initialization Cache Configuration Enabling L1 and L2 cache Access test of CMOS (at Cold boot only) (HLT when an error occurred) Checking battery level of CMOS CheckSum check of CMOS Initializing CMOS data (1) Setting up IRT status (Setting of Boot status and IRT Busy Flag, The bit left is 0) Storing DRAM size Resume branch check Not resuming when a CMOS error occurred (at Cold boot only) Not resuming when status code of resume is not set Checking resume error S3 Return error (ICH) Resume error F17AH Checking CheckSum of SM-RAM Resume error F173H Satellite A50/TECRA A2 Maintenance Manual (960-478) 2-23