HP rp8420 HP 9000 rp8420 Server - User Service Guide, Fifth Edition - Page 27

Main Memory Performance Latency to main memory is an important parameter in determining overall system performance. For a server with memory busses at 125MHz, the latency for a page hit is 8.5 cycles (68ns), the latency for a page closed is 11.5 cycles (92ns), and the latency for a page miss is 14.5 cycles (116ns). Valid Memory Configurations The HP 9000 rp8420 server is capable of supporting as little as 0.5GB of main memory using two 256MB DIMMs installed on one of the cell boards and as much as 256 GB by filling all 16 DIMM slots on all four cell boards with 4GB DIMMs. DIMMs must be loaded in sets of two at specified locations on the cell board. Two DIMMs are called an "echelon," so two echelons would be equivalent to four DIMMs, three echelons would be equivalent to six DIMMs, and so on. The DIMMs must be the same size in an echelon. The DIMMs across all cells in a partition should have identical memory loaded. Figure 1-8 shows the DIMM slot layout on the cell board. See Table 1-3 and Figure 1-8 for DIMM load order and layout on the cell board. A quad, as seen in Figure 1-8, is a grouping of four DIMMs. Configurations with 8 or 16 DIMM slots loaded are recommended. The DIMM sizes in a quad can be different, but the DIMMs in an echelon must be the same size. Table 1-3 DIMM Load Order Number of DIMMs Installed Action Taken 2 DIMMs = 1 Echelon 4 DIMMs = 2 Echelons 6 DIMMs = 3 Echelons 8 DIMMs = 4 Echelons 10 DIMMs = 5 Echelons 12 DIMMs = 6 Echelons 14 DIMMs = 7 Echelons 16 DIMMs = 8 Echelons Install First Add Second Add Third Add Fourth Add Fifth Add Sixth Add Seventh Add Last DIMM Location on Cell Quad Location Board 0A and 0B Quad 0 1A and 1B Quad 1 2A and 2B Quad 2 3A and 3B Quad 3 4A and 4B Quad 0 5A and 5B Quad 1 6A and 6B Quad 2 7A and 7B Quad 3 Detailed HP 9000 rp8420 server Description 27