Cisco ASR1006 Hardware Installation Guide - Page 115

Codec Complexity or Service, Maximum Supported Density per - asr x chassis

Page 115 highlights

Chapter 3 Overview: Cisco ASR 1000 Series Aggregation Services Routers SPAs Cisco DSP SPA for ASR 1000 Series Overview OL-14126-12 Each SPA-DSP comprises of seven SP2603 DSP chips having a total of 21 DSP cores (three DSP cores per SP2603). Based on the complexity of codec (low, medium, high), the density or maximum number of channels supported per DSP core and maximum channels supported per SPA-DSP are defined. Table 3-45 provides a matrix for the maximum number of channels supported on the DSP core and on SPA-DSP, and the complexity type: Table 3-45 Codec Complexity and Density Supported Matrix Maximum Supported Density per Codec Complexity or Service DSP Core LC (Low complexity) 43 Voice/xcode MC (Medium complexity) 28 Voice/xcode HC (High Complexity) 17 Voice/xcode ISAC Voice/xcode 8 Maximum Supported Density per SPA-DSP 903 588 357 168 Table 3-46 provides hardware and software compatibility details for a SPA-DSP. Table 3-46 SPA-DSP Hardware and Software Compatibility Type of DSP SPA (Product ID) SPA-DSP ASR1000 Router Route Chassis Processor Supported Supported ASR 1002, ASR 1004, and ASR 1006 Chassis RP1 and RP2 Power SIPs ESPs Requirements Supported Supported 25 watts SIP-10 and SIP-40 ESP-10 and ESP-40 Minimum Cisco IOS XE Release Supported Cisco IOS XE Release 3.2S The SPA-DSP supports transcoding for the codecs listed in Table 3-47. Table 3-47 SPA-DSP-Supported Transcoding Codec List Codec Name g711alaw g711ulaw g722-64 g723r53 g723r63 g726r16 g726r24 g726r32 g726r40 g728 Codec Description G.711 A Law 64000 bps G.711 u Law 64000 bps G722r64 G.723.1 5300 bps G.723.1 6300 bps G.726 16000 bps G.726 24000 bps G.726 32000 bps G.726 40000 bps G.728 codec Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Hardware Installation Guide 3-73

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188

3-73
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Hardware Installation Guide
OL-14126-12
Chapter 3
Overview: Cisco ASR 1000 Series Aggregation Services Routers SPAs
Cisco DSP SPA for ASR 1000 Series Overview
Each SPA-DSP comprises of seven SP2603 DSP chips having a total of 21 DSP cores (three DSP cores
per SP2603). Based on the complexity of codec (low, medium, high), the density or maximum number
of channels supported per DSP core and maximum channels supported per SPA-DSP are defined.
Table 3-45
provides a matrix for the maximum number of channels supported on the DSP core and on
SPA-DSP, and the complexity type:
Table 3-45
Codec Complexity and Density Supported Matrix
Table 3-46
provides hardware and software compatibility details for a SPA-DSP.
Table 3-46
SPA-DSP Hardware and Software Compatibility
The SPA-DSP supports transcoding for the codecs listed in
Table 3-47
.
Table 3-47
SPA-DSP-Supported Transcoding Codec List
Codec Complexity or Service
Maximum Supported Density per
DSP Core
Maximum Supported Density per
SPA-DSP
LC (Low complexity)
Voice/xcode
43
903
MC (Medium complexity)
Voice/xcode
28
588
HC (High Complexity)
Voice/xcode
17
357
ISAC Voice/xcode
8
168
Type of DSP
SPA (Product
ID)
ASR1000 Router
Chassis
Supported
Route
Processor
Supported
Power
Requirements
SIPs
Supported
ESPs
Supported
Minimum
Cisco IOS XE
Release
Supported
SPA-DSP
ASR 1002,
ASR 1004, and
ASR 1006
Chassis
RP1 and
RP2
25 watts
SIP-10
and
SIP-40
ESP-10
and
ESP-40
Cisco IOS XE
Release 3.2S
Codec Name
Codec Description
g711alaw
G.711 A Law 64000 bps
g711ulaw
G.711 u Law 64000 bps
g722-64
G722r64
g723r53
G.723.1 5300 bps
g723r63
G.723.1 6300 bps
g726r16
G.726 16000 bps
g726r24
G.726 24000 bps
g726r32
G.726 32000 bps
g726r40
G.726 40000 bps
g728
G.728 codec