HP Visualize b180L hp Visualize workstation b132L, b132L plus, b160L, b180L se - Page 112

Table 12 Troubleshooting Dealing with HPMC (Uncorrectable Error) SIMM pair identified in this procedure. Return the system state (for example, FASTBOOT) to the original condition. HPMC Caused by a Data Cache Parity Error An HPMC interruption is forced when a data parity error is detected during a Load instruction to the memory address space or during a data cache flush operation. Table 12 shows an example of the HPMC error information retrieved from Stable Storage by the PIM_INFO command during the Boot Administration environment. Processor Module Error (Data Cache Parity) Word Value Check Type CPU State Cache Check TLB Check Bus Check Assists Check Assists State System Responder Address System Requester Address System Controller Status 0x80000000 0x9e000004 0x40000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000nnn 90